Xenomai  3.0.8
e1000_hw.h
1 /*******************************************************************************
2 
3 
4  Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms of the GNU General Public License as published by the Free
8  Software Foundation; either version 2 of the License, or (at your option)
9  any later version.
10 
11  This program is distributed in the hope that it will be useful, but WITHOUT
12  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14  more details.
15 
16  You should have received a copy of the GNU General Public License along with
17  this program; if not, write to the Free Software Foundation, Inc., 59
18  Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 
20  The full GNU General Public License is included in this distribution in the
21  file called LICENSE.
22 
23  Contact Information:
24  Linux NICS <linux.nics@intel.com>
25  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
26  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 
28 *******************************************************************************/
29 
30 /* e1000_hw.h
31  * Structures, enums, and macros for the MAC
32  */
33 
34 #ifndef _E1000_HW_H_
35 #define _E1000_HW_H_
36 
37 #include "e1000_osdep.h"
38 
39 
40 /* Forward declarations of structures used by the shared code */
41 struct e1000_hw;
42 struct e1000_hw_stats;
43 
44 /* Enumerated types specific to the e1000 hardware */
45 /* Media Access Controlers */
46 typedef enum {
47  e1000_undefined = 0,
48  e1000_82542_rev2_0,
49  e1000_82542_rev2_1,
50  e1000_82543,
51  e1000_82544,
52  e1000_82540,
53  e1000_82545,
54  e1000_82545_rev_3,
55  e1000_82546,
56  e1000_82546_rev_3,
57  e1000_82541,
58  e1000_82541_rev_2,
59  e1000_82547,
60  e1000_82547_rev_2,
61  e1000_82571,
62  e1000_82572,
63  e1000_82573,
64  e1000_80003es2lan,
65  e1000_ich8lan,
66  e1000_num_macs
67 } e1000_mac_type;
68 
69 typedef enum {
70  e1000_eeprom_uninitialized = 0,
71  e1000_eeprom_spi,
72  e1000_eeprom_microwire,
73  e1000_eeprom_flash,
74  e1000_eeprom_ich8,
75  e1000_eeprom_none, /* No NVM support */
76  e1000_num_eeprom_types
77 } e1000_eeprom_type;
78 
79 /* Media Types */
80 typedef enum {
81  e1000_media_type_copper = 0,
82  e1000_media_type_fiber = 1,
83  e1000_media_type_internal_serdes = 2,
84  e1000_num_media_types
85 } e1000_media_type;
86 
87 typedef enum {
88  e1000_10_half = 0,
89  e1000_10_full = 1,
90  e1000_100_half = 2,
91  e1000_100_full = 3
92 } e1000_speed_duplex_type;
93 
94 /* Flow Control Settings */
95 typedef enum {
96  e1000_fc_none = 0,
97  e1000_fc_rx_pause = 1,
98  e1000_fc_tx_pause = 2,
99  e1000_fc_full = 3,
100  e1000_fc_default = 0xFF
101 } e1000_fc_type;
102 
103 struct e1000_shadow_ram {
104  uint16_t eeprom_word;
105  boolean_t modified;
106 };
107 
108 /* PCI bus types */
109 typedef enum {
110  e1000_bus_type_unknown = 0,
111  e1000_bus_type_pci,
112  e1000_bus_type_pcix,
113  e1000_bus_type_pci_express,
114  e1000_bus_type_reserved
115 } e1000_bus_type;
116 
117 /* PCI bus speeds */
118 typedef enum {
119  e1000_bus_speed_unknown = 0,
120  e1000_bus_speed_33,
121  e1000_bus_speed_66,
122  e1000_bus_speed_100,
123  e1000_bus_speed_120,
124  e1000_bus_speed_133,
125  e1000_bus_speed_2500,
126  e1000_bus_speed_reserved
127 } e1000_bus_speed;
128 
129 /* PCI bus widths */
130 typedef enum {
131  e1000_bus_width_unknown = 0,
132  e1000_bus_width_32,
133  e1000_bus_width_64,
134  e1000_bus_width_pciex_1,
135  e1000_bus_width_pciex_2,
136  e1000_bus_width_pciex_4,
137  e1000_bus_width_reserved
138 } e1000_bus_width;
139 
140 /* PHY status info structure and supporting enums */
141 typedef enum {
142  e1000_cable_length_50 = 0,
143  e1000_cable_length_50_80,
144  e1000_cable_length_80_110,
145  e1000_cable_length_110_140,
146  e1000_cable_length_140,
147  e1000_cable_length_undefined = 0xFF
148 } e1000_cable_length;
149 
150 typedef enum {
151  e1000_gg_cable_length_60 = 0,
152  e1000_gg_cable_length_60_115 = 1,
153  e1000_gg_cable_length_115_150 = 2,
154  e1000_gg_cable_length_150 = 4
155 } e1000_gg_cable_length;
156 
157 typedef enum {
158  e1000_igp_cable_length_10 = 10,
159  e1000_igp_cable_length_20 = 20,
160  e1000_igp_cable_length_30 = 30,
161  e1000_igp_cable_length_40 = 40,
162  e1000_igp_cable_length_50 = 50,
163  e1000_igp_cable_length_60 = 60,
164  e1000_igp_cable_length_70 = 70,
165  e1000_igp_cable_length_80 = 80,
166  e1000_igp_cable_length_90 = 90,
167  e1000_igp_cable_length_100 = 100,
168  e1000_igp_cable_length_110 = 110,
169  e1000_igp_cable_length_115 = 115,
170  e1000_igp_cable_length_120 = 120,
171  e1000_igp_cable_length_130 = 130,
172  e1000_igp_cable_length_140 = 140,
173  e1000_igp_cable_length_150 = 150,
174  e1000_igp_cable_length_160 = 160,
175  e1000_igp_cable_length_170 = 170,
176  e1000_igp_cable_length_180 = 180
177 } e1000_igp_cable_length;
178 
179 typedef enum {
180  e1000_10bt_ext_dist_enable_normal = 0,
181  e1000_10bt_ext_dist_enable_lower,
182  e1000_10bt_ext_dist_enable_undefined = 0xFF
183 } e1000_10bt_ext_dist_enable;
184 
185 typedef enum {
186  e1000_rev_polarity_normal = 0,
187  e1000_rev_polarity_reversed,
188  e1000_rev_polarity_undefined = 0xFF
189 } e1000_rev_polarity;
190 
191 typedef enum {
192  e1000_downshift_normal = 0,
193  e1000_downshift_activated,
194  e1000_downshift_undefined = 0xFF
195 } e1000_downshift;
196 
197 typedef enum {
198  e1000_smart_speed_default = 0,
199  e1000_smart_speed_on,
200  e1000_smart_speed_off
201 } e1000_smart_speed;
202 
203 typedef enum {
204  e1000_polarity_reversal_enabled = 0,
205  e1000_polarity_reversal_disabled,
206  e1000_polarity_reversal_undefined = 0xFF
207 } e1000_polarity_reversal;
208 
209 typedef enum {
210  e1000_auto_x_mode_manual_mdi = 0,
211  e1000_auto_x_mode_manual_mdix,
212  e1000_auto_x_mode_auto1,
213  e1000_auto_x_mode_auto2,
214  e1000_auto_x_mode_undefined = 0xFF
215 } e1000_auto_x_mode;
216 
217 typedef enum {
218  e1000_1000t_rx_status_not_ok = 0,
219  e1000_1000t_rx_status_ok,
220  e1000_1000t_rx_status_undefined = 0xFF
221 } e1000_1000t_rx_status;
222 
223 typedef enum {
224  e1000_phy_m88 = 0,
225  e1000_phy_igp,
226  e1000_phy_igp_2,
227  e1000_phy_gg82563,
228  e1000_phy_igp_3,
229  e1000_phy_ife,
230  e1000_phy_undefined = 0xFF
231 } e1000_phy_type;
232 
233 typedef enum {
234  e1000_ms_hw_default = 0,
235  e1000_ms_force_master,
236  e1000_ms_force_slave,
237  e1000_ms_auto
238 } e1000_ms_type;
239 
240 typedef enum {
241  e1000_ffe_config_enabled = 0,
242  e1000_ffe_config_active,
243  e1000_ffe_config_blocked
244 } e1000_ffe_config;
245 
246 typedef enum {
247  e1000_dsp_config_disabled = 0,
248  e1000_dsp_config_enabled,
249  e1000_dsp_config_activated,
250  e1000_dsp_config_undefined = 0xFF
251 } e1000_dsp_config;
252 
253 struct e1000_phy_info {
254  e1000_cable_length cable_length;
255  e1000_10bt_ext_dist_enable extended_10bt_distance;
256  e1000_rev_polarity cable_polarity;
257  e1000_downshift downshift;
258  e1000_polarity_reversal polarity_correction;
259  e1000_auto_x_mode mdix_mode;
260  e1000_1000t_rx_status local_rx;
261  e1000_1000t_rx_status remote_rx;
262 };
263 
264 struct e1000_phy_stats {
265  uint32_t idle_errors;
266  uint32_t receive_errors;
267 };
268 
269 struct e1000_eeprom_info {
270  e1000_eeprom_type type;
271  uint16_t word_size;
272  uint16_t opcode_bits;
273  uint16_t address_bits;
274  uint16_t delay_usec;
275  uint16_t page_size;
276  boolean_t use_eerd;
277  boolean_t use_eewr;
278 };
279 
280 /* Flex ASF Information */
281 #define E1000_HOST_IF_MAX_SIZE 2048
282 
283 typedef enum {
284  e1000_byte_align = 0,
285  e1000_word_align = 1,
286  e1000_dword_align = 2
287 } e1000_align_type;
288 
289 
290 
291 /* Error Codes */
292 #define E1000_SUCCESS 0
293 #define E1000_ERR_EEPROM 1
294 #define E1000_ERR_PHY 2
295 #define E1000_ERR_CONFIG 3
296 #define E1000_ERR_PARAM 4
297 #define E1000_ERR_MAC_TYPE 5
298 #define E1000_ERR_PHY_TYPE 6
299 #define E1000_ERR_RESET 9
300 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
301 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
302 #define E1000_BLK_PHY_RESET 12
303 #define E1000_ERR_SWFW_SYNC 13
304 
305 /* Function prototypes */
306 /* Initialization */
307 int32_t e1000_reset_hw(struct e1000_hw *hw);
308 int32_t e1000_init_hw(struct e1000_hw *hw);
309 int32_t e1000_id_led_init(struct e1000_hw * hw);
310 int32_t e1000_set_mac_type(struct e1000_hw *hw);
311 void e1000_set_media_type(struct e1000_hw *hw);
312 
313 /* Link Configuration */
314 int32_t e1000_setup_link(struct e1000_hw *hw);
315 int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
316 void e1000_config_collision_dist(struct e1000_hw *hw);
317 int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
318 int32_t e1000_check_for_link(struct e1000_hw *hw);
319 int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex);
320 int32_t e1000_wait_autoneg(struct e1000_hw *hw);
321 int32_t e1000_force_mac_fc(struct e1000_hw *hw);
322 
323 /* PHY */
324 int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
325 int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
326 int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
327 int32_t e1000_phy_reset(struct e1000_hw *hw);
328 void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
329 int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
330 int32_t e1000_duplex_reversal(struct e1000_hw *hw);
331 int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
332 int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
333 int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
334 int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
335 int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
336 int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
337 int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
338 int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
339 int32_t e1000_check_downshift(struct e1000_hw *hw);
340 int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
341 int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
342 int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
343 
344 /* EEPROM Functions */
345 int32_t e1000_init_eeprom_params(struct e1000_hw *hw);
346 boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
347 int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
348 int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
349 int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
350 
351 /* MNG HOST IF functions */
352 uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
353 
354 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
355 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
356 
357 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
358 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
359 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
360 #define E1000_MNG_IAMT_MODE 0x3
361 #define E1000_MNG_ICH_IAMT_MODE 0x2
362 #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
363 
364 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
365 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
366 #define E1000_VFTA_ENTRY_SHIFT 0x5
367 #define E1000_VFTA_ENTRY_MASK 0x7F
368 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
369 
370 struct e1000_host_mng_command_header {
371  uint8_t command_id;
372  uint8_t checksum;
373  uint16_t reserved1;
374  uint16_t reserved2;
375  uint16_t command_length;
376 };
377 
378 struct e1000_host_mng_command_info {
379  struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
380  uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/
381 };
382 #ifdef E1000_BIG_ENDIAN
383 struct e1000_host_mng_dhcp_cookie{
384  uint32_t signature;
385  uint16_t vlan_id;
386  uint8_t reserved0;
387  uint8_t status;
388  uint32_t reserved1;
389  uint8_t checksum;
390  uint8_t reserved3;
391  uint16_t reserved2;
392 };
393 #else
394 struct e1000_host_mng_dhcp_cookie{
395  uint32_t signature;
396  uint8_t status;
397  uint8_t reserved0;
398  uint16_t vlan_id;
399  uint32_t reserved1;
400  uint16_t reserved2;
401  uint8_t reserved3;
402  uint8_t checksum;
403 };
404 #endif
405 
406 int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
407  uint16_t length);
408 boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
409 boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
410 int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
411 int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer,
412  uint16_t length, uint16_t offset, uint8_t *sum);
413 int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw,
414  struct e1000_host_mng_command_header* hdr);
415 
416 int32_t e1000_mng_write_commit(struct e1000_hw *hw);
417 
418 int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
419 int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
420 int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
421 int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
422 int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
423 int32_t e1000_read_mac_addr(struct e1000_hw * hw);
424 int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
425 void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
426 void e1000_release_software_flag(struct e1000_hw *hw);
427 int32_t e1000_get_software_flag(struct e1000_hw *hw);
428 
429 /* Filters (multicast, vlan, receive) */
430 void e1000_init_rx_addrs(struct e1000_hw *hw);
431 void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
432 uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
433 void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
434 void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
435 void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
436 void e1000_clear_vfta(struct e1000_hw *hw);
437 
438 /* LED functions */
439 int32_t e1000_setup_led(struct e1000_hw *hw);
440 int32_t e1000_cleanup_led(struct e1000_hw *hw);
441 int32_t e1000_led_on(struct e1000_hw *hw);
442 int32_t e1000_led_off(struct e1000_hw *hw);
443 int32_t e1000_blink_led_start(struct e1000_hw *hw);
444 
445 /* Adaptive IFS Functions */
446 
447 /* Everything else */
448 void e1000_clear_hw_cntrs(struct e1000_hw *hw);
449 void e1000_reset_adaptive(struct e1000_hw *hw);
450 void e1000_update_adaptive(struct e1000_hw *hw);
451 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
452 void e1000_get_bus_info(struct e1000_hw *hw);
453 void e1000_pci_set_mwi(struct e1000_hw *hw);
454 void e1000_pci_clear_mwi(struct e1000_hw *hw);
455 void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
456 void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
457 /* Port I/O is only supported on 82544 and newer */
458 uint32_t e1000_io_read(struct e1000_hw *hw, unsigned long port);
459 uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
460 void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
461 void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
462 int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
463 int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
464 int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
465 void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
466 void e1000_enable_pciex_master(struct e1000_hw *hw);
467 int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
468 int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
469 int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
470 int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
471 void e1000_release_software_semaphore(struct e1000_hw *hw);
472 int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
473 int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
474 void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
475 int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
476 uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
477 int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
478 
479 int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index,
480  uint8_t *data);
481 int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
482  uint8_t byte);
483 int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
484  uint8_t byte);
485 int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index,
486  uint16_t *data);
487 int32_t e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index,
488  uint16_t word);
489 int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
490  uint32_t size, uint16_t *data);
491 int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index,
492  uint32_t size, uint16_t data);
493 int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
494  uint16_t words, uint16_t *data);
495 int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
496  uint16_t words, uint16_t *data);
497 int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment);
498 int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
499 int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
500 int32_t e1000_phy_ife_get_info(struct e1000_hw *hw,
501  struct e1000_phy_info *phy_info);
502 int32_t e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw);
503 int32_t e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw);
504 
505 #define E1000_READ_REG_IO(a, reg) \
506  e1000_read_reg_io((a), E1000_##reg)
507 #define E1000_WRITE_REG_IO(a, reg, val) \
508  e1000_write_reg_io((a), E1000_##reg, val)
509 
510 /* PCI Device IDs */
511 #define E1000_DEV_ID_82542 0x1000
512 #define E1000_DEV_ID_82543GC_FIBER 0x1001
513 #define E1000_DEV_ID_82543GC_COPPER 0x1004
514 #define E1000_DEV_ID_82544EI_COPPER 0x1008
515 #define E1000_DEV_ID_82544EI_FIBER 0x1009
516 #define E1000_DEV_ID_82544GC_COPPER 0x100C
517 #define E1000_DEV_ID_82544GC_LOM 0x100D
518 #define E1000_DEV_ID_82540EM 0x100E
519 #define E1000_DEV_ID_82540EM_LOM 0x1015
520 #define E1000_DEV_ID_82540EP_LOM 0x1016
521 #define E1000_DEV_ID_82540EP 0x1017
522 #define E1000_DEV_ID_82540EP_LP 0x101E
523 #define E1000_DEV_ID_82545EM_COPPER 0x100F
524 #define E1000_DEV_ID_82545EM_FIBER 0x1011
525 #define E1000_DEV_ID_82545GM_COPPER 0x1026
526 #define E1000_DEV_ID_82545GM_FIBER 0x1027
527 #define E1000_DEV_ID_82545GM_SERDES 0x1028
528 #define E1000_DEV_ID_82546EB_COPPER 0x1010
529 #define E1000_DEV_ID_82546EB_FIBER 0x1012
530 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
531 #define E1000_DEV_ID_82541EI 0x1013
532 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
533 #define E1000_DEV_ID_82541ER_LOM 0x1014
534 #define E1000_DEV_ID_82541ER 0x1078
535 #define E1000_DEV_ID_82547GI 0x1075
536 #define E1000_DEV_ID_82541GI 0x1076
537 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
538 #define E1000_DEV_ID_82541GI_LF 0x107C
539 #define E1000_DEV_ID_82546GB_COPPER 0x1079
540 #define E1000_DEV_ID_82546GB_FIBER 0x107A
541 #define E1000_DEV_ID_82546GB_SERDES 0x107B
542 #define E1000_DEV_ID_82546GB_PCIE 0x108A
543 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
544 #define E1000_DEV_ID_82547EI 0x1019
545 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
546 #define E1000_DEV_ID_82571EB_COPPER 0x105E
547 #define E1000_DEV_ID_82571EB_FIBER 0x105F
548 #define E1000_DEV_ID_82571EB_SERDES 0x1060
549 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
550 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
551 #define E1000_DEV_ID_82572EI_COPPER 0x107D
552 #define E1000_DEV_ID_82572EI_FIBER 0x107E
553 #define E1000_DEV_ID_82572EI_SERDES 0x107F
554 #define E1000_DEV_ID_82572EI 0x10B9
555 #define E1000_DEV_ID_82573E 0x108B
556 #define E1000_DEV_ID_82573E_IAMT 0x108C
557 #define E1000_DEV_ID_82573L 0x109A
558 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
559 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
560 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
561 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
562 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
563 
564 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
565 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
566 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
567 #define E1000_DEV_ID_ICH8_IFE 0x104C
568 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
569 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
570 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
571 
572 
573 #define NODE_ADDRESS_SIZE 6
574 #define ETH_LENGTH_OF_ADDRESS 6
575 
576 /* MAC decode size is 128K - This is the size of BAR0 */
577 #define MAC_DECODE_SIZE (128 * 1024)
578 
579 #define E1000_82542_2_0_REV_ID 2
580 #define E1000_82542_2_1_REV_ID 3
581 #define E1000_REVISION_0 0
582 #define E1000_REVISION_1 1
583 #define E1000_REVISION_2 2
584 #define E1000_REVISION_3 3
585 
586 #define SPEED_10 10
587 #define SPEED_100 100
588 #define SPEED_1000 1000
589 #define HALF_DUPLEX 1
590 #define FULL_DUPLEX 2
591 
592 /* The sizes (in bytes) of a ethernet packet */
593 #define ENET_HEADER_SIZE 14
594 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
595 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
596 #define ETHERNET_FCS_SIZE 4
597 #define MAXIMUM_ETHERNET_PACKET_SIZE \
598  (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
599 #define MINIMUM_ETHERNET_PACKET_SIZE \
600  (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
601 #define CRC_LENGTH ETHERNET_FCS_SIZE
602 #define MAX_JUMBO_FRAME_SIZE 0x3F00
603 
604 
605 /* 802.1q VLAN Packet Sizes */
606 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
607 
608 /* Ethertype field values */
609 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
610 #define ETHERNET_IP_TYPE 0x0800 /* IP packets */
611 #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
612 
613 /* Packet Header defines */
614 #define IP_PROTOCOL_TCP 6
615 #define IP_PROTOCOL_UDP 0x11
616 
617 /* This defines the bits that are set in the Interrupt Mask
618  * Set/Read Register. Each bit is documented below:
619  * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
620  * o RXSEQ = Receive Sequence Error
621  */
622 #define POLL_IMS_ENABLE_MASK ( \
623  E1000_IMS_RXDMT0 | \
624  E1000_IMS_RXSEQ)
625 
626 /* This defines the bits that are set in the Interrupt Mask
627  * Set/Read Register. Each bit is documented below:
628  * o RXT0 = Receiver Timer Interrupt (ring 0)
629  * o TXDW = Transmit Descriptor Written Back
630  * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
631  * o RXSEQ = Receive Sequence Error
632  * o LSC = Link Status Change
633  */
634 #define IMS_ENABLE_MASK ( \
635  E1000_IMS_RXT0 | \
636  E1000_IMS_TXDW | \
637  E1000_IMS_RXDMT0 | \
638  E1000_IMS_RXSEQ | \
639  E1000_IMS_LSC)
640 
641 /* Additional interrupts need to be handled for e1000_ich8lan:
642  DSW = The FW changed the status of the DISSW bit in FWSM
643  PHYINT = The LAN connected device generates an interrupt
644  EPRST = Manageability reset event */
645 #define IMS_ICH8LAN_ENABLE_MASK (\
646  E1000_IMS_DSW | \
647  E1000_IMS_PHYINT | \
648  E1000_IMS_EPRST)
649 
650 /* Number of high/low register pairs in the RAR. The RAR (Receive Address
651  * Registers) holds the directed and multicast addresses that we monitor. We
652  * reserve one of these spots for our directed address, allowing us room for
653  * E1000_RAR_ENTRIES - 1 multicast addresses.
654  */
655 #define E1000_RAR_ENTRIES 15
656 #define E1000_RAR_ENTRIES_ICH8LAN 7
657 
658 #define MIN_NUMBER_OF_DESCRIPTORS 8
659 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
660 
661 /* Receive Descriptor */
662 struct e1000_rx_desc {
663  uint64_t buffer_addr; /* Address of the descriptor's data buffer */
664  uint16_t length; /* Length of data DMAed into data buffer */
665  uint16_t csum; /* Packet checksum */
666  uint8_t status; /* Descriptor status */
667  uint8_t errors; /* Descriptor Errors */
668  uint16_t special;
669 };
670 
671 /* Receive Descriptor - Extended */
672 union e1000_rx_desc_extended {
673  struct {
674  uint64_t buffer_addr;
675  uint64_t reserved;
676  } read;
677  struct {
678  struct {
679  uint32_t mrq; /* Multiple Rx Queues */
680  union {
681  uint32_t rss; /* RSS Hash */
682  struct {
683  uint16_t ip_id; /* IP id */
684  uint16_t csum; /* Packet Checksum */
685  } csum_ip;
686  } hi_dword;
687  } lower;
688  struct {
689  uint32_t status_error; /* ext status/error */
690  uint16_t length;
691  uint16_t vlan; /* VLAN tag */
692  } upper;
693  } wb; /* writeback */
694 };
695 
696 #define MAX_PS_BUFFERS 4
697 /* Receive Descriptor - Packet Split */
698 union e1000_rx_desc_packet_split {
699  struct {
700  /* one buffer for protocol header(s), three data buffers */
701  uint64_t buffer_addr[MAX_PS_BUFFERS];
702  } read;
703  struct {
704  struct {
705  uint32_t mrq; /* Multiple Rx Queues */
706  union {
707  uint32_t rss; /* RSS Hash */
708  struct {
709  uint16_t ip_id; /* IP id */
710  uint16_t csum; /* Packet Checksum */
711  } csum_ip;
712  } hi_dword;
713  } lower;
714  struct {
715  uint32_t status_error; /* ext status/error */
716  uint16_t length0; /* length of buffer 0 */
717  uint16_t vlan; /* VLAN tag */
718  } middle;
719  struct {
720  uint16_t header_status;
721  uint16_t length[3]; /* length of buffers 1-3 */
722  } upper;
723  uint64_t reserved;
724  } wb; /* writeback */
725 };
726 
727 /* Receive Decriptor bit definitions */
728 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
729 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
730 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
731 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
732 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
733 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
734 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
735 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
736 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
737 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
738 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
739 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
740 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
741 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
742 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
743 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
744 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
745 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
746 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
747 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
748 #define E1000_RXD_SPC_PRI_SHIFT 13
749 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
750 #define E1000_RXD_SPC_CFI_SHIFT 12
751 
752 #define E1000_RXDEXT_STATERR_CE 0x01000000
753 #define E1000_RXDEXT_STATERR_SE 0x02000000
754 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
755 #define E1000_RXDEXT_STATERR_CXE 0x10000000
756 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
757 #define E1000_RXDEXT_STATERR_IPE 0x40000000
758 #define E1000_RXDEXT_STATERR_RXE 0x80000000
759 
760 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
761 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
762 
763 /* mask to determine if packets should be dropped due to frame errors */
764 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
765  E1000_RXD_ERR_CE | \
766  E1000_RXD_ERR_SE | \
767  E1000_RXD_ERR_SEQ | \
768  E1000_RXD_ERR_CXE | \
769  E1000_RXD_ERR_RXE)
770 
771 
772 /* Same mask, but for extended and packet split descriptors */
773 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
774  E1000_RXDEXT_STATERR_CE | \
775  E1000_RXDEXT_STATERR_SE | \
776  E1000_RXDEXT_STATERR_SEQ | \
777  E1000_RXDEXT_STATERR_CXE | \
778  E1000_RXDEXT_STATERR_RXE)
779 
780 /* Transmit Descriptor */
781 struct e1000_tx_desc {
782  uint64_t buffer_addr; /* Address of the descriptor's data buffer */
783  union {
784  uint32_t data;
785  struct {
786  uint16_t length; /* Data buffer length */
787  uint8_t cso; /* Checksum offset */
788  uint8_t cmd; /* Descriptor control */
789  } flags;
790  } lower;
791  union {
792  uint32_t data;
793  struct {
794  uint8_t status; /* Descriptor status */
795  uint8_t css; /* Checksum start */
796  uint16_t special;
797  } fields;
798  } upper;
799 };
800 
801 /* Transmit Descriptor bit definitions */
802 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
803 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
804 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
805 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
806 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
807 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
808 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
809 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
810 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
811 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
812 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
813 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
814 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
815 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
816 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
817 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
818 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
819 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
820 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
821 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
822 
823 /* Offload Context Descriptor */
824 struct e1000_context_desc {
825  union {
826  uint32_t ip_config;
827  struct {
828  uint8_t ipcss; /* IP checksum start */
829  uint8_t ipcso; /* IP checksum offset */
830  uint16_t ipcse; /* IP checksum end */
831  } ip_fields;
832  } lower_setup;
833  union {
834  uint32_t tcp_config;
835  struct {
836  uint8_t tucss; /* TCP checksum start */
837  uint8_t tucso; /* TCP checksum offset */
838  uint16_t tucse; /* TCP checksum end */
839  } tcp_fields;
840  } upper_setup;
841  uint32_t cmd_and_length; /* */
842  union {
843  uint32_t data;
844  struct {
845  uint8_t status; /* Descriptor status */
846  uint8_t hdr_len; /* Header length */
847  uint16_t mss; /* Maximum segment size */
848  } fields;
849  } tcp_seg_setup;
850 };
851 
852 /* Offload data descriptor */
853 struct e1000_data_desc {
854  uint64_t buffer_addr; /* Address of the descriptor's buffer address */
855  union {
856  uint32_t data;
857  struct {
858  uint16_t length; /* Data buffer length */
859  uint8_t typ_len_ext; /* */
860  uint8_t cmd; /* */
861  } flags;
862  } lower;
863  union {
864  uint32_t data;
865  struct {
866  uint8_t status; /* Descriptor status */
867  uint8_t popts; /* Packet Options */
868  uint16_t special; /* */
869  } fields;
870  } upper;
871 };
872 
873 /* Filters */
874 #define E1000_NUM_UNICAST 16 /* Unicast filter entries */
875 #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
876 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
877 
878 #define E1000_NUM_UNICAST_ICH8LAN 7
879 #define E1000_MC_TBL_SIZE_ICH8LAN 32
880 
881 
882 /* Receive Address Register */
883 struct e1000_rar {
884  volatile uint32_t low; /* receive address low */
885  volatile uint32_t high; /* receive address high */
886 };
887 
888 /* Number of entries in the Multicast Table Array (MTA). */
889 #define E1000_NUM_MTA_REGISTERS 128
890 #define E1000_NUM_MTA_REGISTERS_ICH8LAN 32
891 
892 /* IPv4 Address Table Entry */
893 struct e1000_ipv4_at_entry {
894  volatile uint32_t ipv4_addr; /* IP Address (RW) */
895  volatile uint32_t reserved;
896 };
897 
898 /* Four wakeup IP addresses are supported */
899 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
900 #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
901 #define E1000_IP4AT_SIZE_ICH8LAN 3
902 #define E1000_IP6AT_SIZE 1
903 
904 /* IPv6 Address Table Entry */
905 struct e1000_ipv6_at_entry {
906  volatile uint8_t ipv6_addr[16];
907 };
908 
909 /* Flexible Filter Length Table Entry */
910 struct e1000_fflt_entry {
911  volatile uint32_t length; /* Flexible Filter Length (RW) */
912  volatile uint32_t reserved;
913 };
914 
915 /* Flexible Filter Mask Table Entry */
916 struct e1000_ffmt_entry {
917  volatile uint32_t mask; /* Flexible Filter Mask (RW) */
918  volatile uint32_t reserved;
919 };
920 
921 /* Flexible Filter Value Table Entry */
922 struct e1000_ffvt_entry {
923  volatile uint32_t value; /* Flexible Filter Value (RW) */
924  volatile uint32_t reserved;
925 };
926 
927 /* Four Flexible Filters are supported */
928 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
929 
930 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
931 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
932 
933 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
934 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
935 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
936 
937 #define E1000_DISABLE_SERDES_LOOPBACK 0x0400
938 
939 /* Register Set. (82543, 82544)
940  *
941  * Registers are defined to be 32 bits and should be accessed as 32 bit values.
942  * These registers are physically located on the NIC, but are mapped into the
943  * host memory address space.
944  *
945  * RW - register is both readable and writable
946  * RO - register is read only
947  * WO - register is write only
948  * R/clr - register is read only and is cleared when read
949  * A - register array
950  */
951 #define E1000_CTRL 0x00000 /* Device Control - RW */
952 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
953 #define E1000_STATUS 0x00008 /* Device Status - RO */
954 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
955 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
956 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
957 #define E1000_FLA 0x0001C /* Flash Access - RW */
958 #define E1000_MDIC 0x00020 /* MDI Control - RW */
959 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
960 #define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
961 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
962 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
963 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
964 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
965 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
966 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
967 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
968 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
969 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
970 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
971 #define E1000_RCTL 0x00100 /* RX Control - RW */
972 #define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
973 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
974 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
975 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
976 #define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
977 #define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
978 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
979 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
980 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
981 #define E1000_TCTL 0x00400 /* TX Control - RW */
982 #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
983 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
984 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */
985 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
986 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
987 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
988 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
989 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
990 #define FEXTNVM_SW_CONFIG 0x0001
991 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
992 #define E1000_PBS 0x01008 /* Packet Buffer Size */
993 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
994 #define E1000_FLASH_UPDATES 1000
995 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
996 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */
997 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
998 #define E1000_FLSWCTL 0x01030 /* FLASH control register */
999 #define E1000_FLSWDATA 0x01034 /* FLASH data register */
1000 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
1001 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */
1002 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
1003 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
1004 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
1005 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
1006 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
1007 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
1008 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
1009 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
1010 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
1011 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
1012 #define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
1013 #define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
1014 #define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
1015 #define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
1016 #define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
1017 #define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
1018 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
1019 #define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
1020 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
1021 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
1022 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
1023 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
1024 #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
1025 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
1026 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
1027 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
1028 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
1029 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
1030 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
1031 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
1032 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
1033 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
1034 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
1035 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
1036 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
1037 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
1038 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
1039 #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
1040 #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
1041 #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
1042 #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
1043 #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
1044 #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
1045 #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
1046 #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
1047 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
1048 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
1049 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
1050 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
1051 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
1052 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
1053 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
1054 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
1055 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
1056 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
1057 #define E1000_DC 0x04030 /* Defer Count - R/clr */
1058 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
1059 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
1060 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
1061 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
1062 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
1063 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
1064 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
1065 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
1066 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
1067 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
1068 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
1069 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
1070 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
1071 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
1072 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
1073 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
1074 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
1075 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
1076 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
1077 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
1078 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
1079 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
1080 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
1081 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
1082 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
1083 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
1084 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
1085 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
1086 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
1087 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
1088 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
1089 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
1090 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
1091 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
1092 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
1093 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
1094 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
1095 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
1096 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
1097 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
1098 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
1099 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
1100 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
1101 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
1102 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
1103 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
1104 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
1105 #define E1000_IAC 0x04100 /* Interrupt Assertion Count */
1106 #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
1107 #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
1108 #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
1109 #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
1110 #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
1111 #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
1112 #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
1113 #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
1114 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
1115 #define E1000_RFCTL 0x05008 /* Receive Filter Control*/
1116 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
1117 #define E1000_RA 0x05400 /* Receive Address - RW Array */
1118 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
1119 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
1120 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
1121 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
1122 #define E1000_MANC 0x05820 /* Management Control - RW */
1123 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
1124 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
1125 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
1126 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
1127 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
1128 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
1129 #define E1000_HOST_IF 0x08800 /* Host Interface */
1130 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
1131 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
1132 
1133 #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
1134 #define E1000_MDPHYA 0x0003C /* PHY address - RW */
1135 #define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */
1136 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
1137 
1138 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
1139 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1140 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1141 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1142 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1143 #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1144 #define E1000_SWSM 0x05B50 /* SW Semaphore */
1145 #define E1000_FWSM 0x05B54 /* FW Semaphore */
1146 #define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1147 #define E1000_HICR 0x08F00 /* Host Inteface Control */
1148 
1149 /* RSS registers */
1150 #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1151 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1152 #define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1153 #define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1154 #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
1155 #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
1156 /* Register Set (82542)
1157  *
1158  * Some of the 82542 registers are located at different offsets than they are
1159  * in more current versions of the 8254x. Despite the difference in location,
1160  * the registers function in the same manner.
1161  */
1162 #define E1000_82542_CTRL E1000_CTRL
1163 #define E1000_82542_CTRL_DUP E1000_CTRL_DUP
1164 #define E1000_82542_STATUS E1000_STATUS
1165 #define E1000_82542_EECD E1000_EECD
1166 #define E1000_82542_EERD E1000_EERD
1167 #define E1000_82542_CTRL_EXT E1000_CTRL_EXT
1168 #define E1000_82542_FLA E1000_FLA
1169 #define E1000_82542_MDIC E1000_MDIC
1170 #define E1000_82542_SCTL E1000_SCTL
1171 #define E1000_82542_FEXTNVM E1000_FEXTNVM
1172 #define E1000_82542_FCAL E1000_FCAL
1173 #define E1000_82542_FCAH E1000_FCAH
1174 #define E1000_82542_FCT E1000_FCT
1175 #define E1000_82542_VET E1000_VET
1176 #define E1000_82542_RA 0x00040
1177 #define E1000_82542_ICR E1000_ICR
1178 #define E1000_82542_ITR E1000_ITR
1179 #define E1000_82542_ICS E1000_ICS
1180 #define E1000_82542_IMS E1000_IMS
1181 #define E1000_82542_IMC E1000_IMC
1182 #define E1000_82542_RCTL E1000_RCTL
1183 #define E1000_82542_RDTR 0x00108
1184 #define E1000_82542_RDBAL 0x00110
1185 #define E1000_82542_RDBAH 0x00114
1186 #define E1000_82542_RDLEN 0x00118
1187 #define E1000_82542_RDH 0x00120
1188 #define E1000_82542_RDT 0x00128
1189 #define E1000_82542_RDTR0 E1000_82542_RDTR
1190 #define E1000_82542_RDBAL0 E1000_82542_RDBAL
1191 #define E1000_82542_RDBAH0 E1000_82542_RDBAH
1192 #define E1000_82542_RDLEN0 E1000_82542_RDLEN
1193 #define E1000_82542_RDH0 E1000_82542_RDH
1194 #define E1000_82542_RDT0 E1000_82542_RDT
1195 #define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
1196  * RX Control - RW */
1197 #define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1198 #define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1199 #define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1200 #define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1201 #define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1202 #define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1203 #define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1204 #define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1205 #define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1206 #define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1207 #define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
1208 #define E1000_82542_RDTR1 0x00130
1209 #define E1000_82542_RDBAL1 0x00138
1210 #define E1000_82542_RDBAH1 0x0013C
1211 #define E1000_82542_RDLEN1 0x00140
1212 #define E1000_82542_RDH1 0x00148
1213 #define E1000_82542_RDT1 0x00150
1214 #define E1000_82542_FCRTH 0x00160
1215 #define E1000_82542_FCRTL 0x00168
1216 #define E1000_82542_FCTTV E1000_FCTTV
1217 #define E1000_82542_TXCW E1000_TXCW
1218 #define E1000_82542_RXCW E1000_RXCW
1219 #define E1000_82542_MTA 0x00200
1220 #define E1000_82542_TCTL E1000_TCTL
1221 #define E1000_82542_TCTL_EXT E1000_TCTL_EXT
1222 #define E1000_82542_TIPG E1000_TIPG
1223 #define E1000_82542_TDBAL 0x00420
1224 #define E1000_82542_TDBAH 0x00424
1225 #define E1000_82542_TDLEN 0x00428
1226 #define E1000_82542_TDH 0x00430
1227 #define E1000_82542_TDT 0x00438
1228 #define E1000_82542_TIDV 0x00440
1229 #define E1000_82542_TBT E1000_TBT
1230 #define E1000_82542_AIT E1000_AIT
1231 #define E1000_82542_VFTA 0x00600
1232 #define E1000_82542_LEDCTL E1000_LEDCTL
1233 #define E1000_82542_PBA E1000_PBA
1234 #define E1000_82542_PBS E1000_PBS
1235 #define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1236 #define E1000_82542_EEARBC E1000_EEARBC
1237 #define E1000_82542_FLASHT E1000_FLASHT
1238 #define E1000_82542_EEWR E1000_EEWR
1239 #define E1000_82542_FLSWCTL E1000_FLSWCTL
1240 #define E1000_82542_FLSWDATA E1000_FLSWDATA
1241 #define E1000_82542_FLSWCNT E1000_FLSWCNT
1242 #define E1000_82542_FLOP E1000_FLOP
1243 #define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1244 #define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1245 #define E1000_82542_PHY_CTRL E1000_PHY_CTRL
1246 #define E1000_82542_ERT E1000_ERT
1247 #define E1000_82542_RXDCTL E1000_RXDCTL
1248 #define E1000_82542_RXDCTL1 E1000_RXDCTL1
1249 #define E1000_82542_RADV E1000_RADV
1250 #define E1000_82542_RSRPD E1000_RSRPD
1251 #define E1000_82542_TXDMAC E1000_TXDMAC
1252 #define E1000_82542_KABGTXD E1000_KABGTXD
1253 #define E1000_82542_TDFHS E1000_TDFHS
1254 #define E1000_82542_TDFTS E1000_TDFTS
1255 #define E1000_82542_TDFPC E1000_TDFPC
1256 #define E1000_82542_TXDCTL E1000_TXDCTL
1257 #define E1000_82542_TADV E1000_TADV
1258 #define E1000_82542_TSPMT E1000_TSPMT
1259 #define E1000_82542_CRCERRS E1000_CRCERRS
1260 #define E1000_82542_ALGNERRC E1000_ALGNERRC
1261 #define E1000_82542_SYMERRS E1000_SYMERRS
1262 #define E1000_82542_RXERRC E1000_RXERRC
1263 #define E1000_82542_MPC E1000_MPC
1264 #define E1000_82542_SCC E1000_SCC
1265 #define E1000_82542_ECOL E1000_ECOL
1266 #define E1000_82542_MCC E1000_MCC
1267 #define E1000_82542_LATECOL E1000_LATECOL
1268 #define E1000_82542_COLC E1000_COLC
1269 #define E1000_82542_DC E1000_DC
1270 #define E1000_82542_TNCRS E1000_TNCRS
1271 #define E1000_82542_SEC E1000_SEC
1272 #define E1000_82542_CEXTERR E1000_CEXTERR
1273 #define E1000_82542_RLEC E1000_RLEC
1274 #define E1000_82542_XONRXC E1000_XONRXC
1275 #define E1000_82542_XONTXC E1000_XONTXC
1276 #define E1000_82542_XOFFRXC E1000_XOFFRXC
1277 #define E1000_82542_XOFFTXC E1000_XOFFTXC
1278 #define E1000_82542_FCRUC E1000_FCRUC
1279 #define E1000_82542_PRC64 E1000_PRC64
1280 #define E1000_82542_PRC127 E1000_PRC127
1281 #define E1000_82542_PRC255 E1000_PRC255
1282 #define E1000_82542_PRC511 E1000_PRC511
1283 #define E1000_82542_PRC1023 E1000_PRC1023
1284 #define E1000_82542_PRC1522 E1000_PRC1522
1285 #define E1000_82542_GPRC E1000_GPRC
1286 #define E1000_82542_BPRC E1000_BPRC
1287 #define E1000_82542_MPRC E1000_MPRC
1288 #define E1000_82542_GPTC E1000_GPTC
1289 #define E1000_82542_GORCL E1000_GORCL
1290 #define E1000_82542_GORCH E1000_GORCH
1291 #define E1000_82542_GOTCL E1000_GOTCL
1292 #define E1000_82542_GOTCH E1000_GOTCH
1293 #define E1000_82542_RNBC E1000_RNBC
1294 #define E1000_82542_RUC E1000_RUC
1295 #define E1000_82542_RFC E1000_RFC
1296 #define E1000_82542_ROC E1000_ROC
1297 #define E1000_82542_RJC E1000_RJC
1298 #define E1000_82542_MGTPRC E1000_MGTPRC
1299 #define E1000_82542_MGTPDC E1000_MGTPDC
1300 #define E1000_82542_MGTPTC E1000_MGTPTC
1301 #define E1000_82542_TORL E1000_TORL
1302 #define E1000_82542_TORH E1000_TORH
1303 #define E1000_82542_TOTL E1000_TOTL
1304 #define E1000_82542_TOTH E1000_TOTH
1305 #define E1000_82542_TPR E1000_TPR
1306 #define E1000_82542_TPT E1000_TPT
1307 #define E1000_82542_PTC64 E1000_PTC64
1308 #define E1000_82542_PTC127 E1000_PTC127
1309 #define E1000_82542_PTC255 E1000_PTC255
1310 #define E1000_82542_PTC511 E1000_PTC511
1311 #define E1000_82542_PTC1023 E1000_PTC1023
1312 #define E1000_82542_PTC1522 E1000_PTC1522
1313 #define E1000_82542_MPTC E1000_MPTC
1314 #define E1000_82542_BPTC E1000_BPTC
1315 #define E1000_82542_TSCTC E1000_TSCTC
1316 #define E1000_82542_TSCTFC E1000_TSCTFC
1317 #define E1000_82542_RXCSUM E1000_RXCSUM
1318 #define E1000_82542_WUC E1000_WUC
1319 #define E1000_82542_WUFC E1000_WUFC
1320 #define E1000_82542_WUS E1000_WUS
1321 #define E1000_82542_MANC E1000_MANC
1322 #define E1000_82542_IPAV E1000_IPAV
1323 #define E1000_82542_IP4AT E1000_IP4AT
1324 #define E1000_82542_IP6AT E1000_IP6AT
1325 #define E1000_82542_WUPL E1000_WUPL
1326 #define E1000_82542_WUPM E1000_WUPM
1327 #define E1000_82542_FFLT E1000_FFLT
1328 #define E1000_82542_TDFH 0x08010
1329 #define E1000_82542_TDFT 0x08018
1330 #define E1000_82542_FFMT E1000_FFMT
1331 #define E1000_82542_FFVT E1000_FFVT
1332 #define E1000_82542_HOST_IF E1000_HOST_IF
1333 #define E1000_82542_IAM E1000_IAM
1334 #define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1335 #define E1000_82542_PSRCTL E1000_PSRCTL
1336 #define E1000_82542_RAID E1000_RAID
1337 #define E1000_82542_TARC0 E1000_TARC0
1338 #define E1000_82542_TDBAL1 E1000_TDBAL1
1339 #define E1000_82542_TDBAH1 E1000_TDBAH1
1340 #define E1000_82542_TDLEN1 E1000_TDLEN1
1341 #define E1000_82542_TDH1 E1000_TDH1
1342 #define E1000_82542_TDT1 E1000_TDT1
1343 #define E1000_82542_TXDCTL1 E1000_TXDCTL1
1344 #define E1000_82542_TARC1 E1000_TARC1
1345 #define E1000_82542_RFCTL E1000_RFCTL
1346 #define E1000_82542_GCR E1000_GCR
1347 #define E1000_82542_GSCL_1 E1000_GSCL_1
1348 #define E1000_82542_GSCL_2 E1000_GSCL_2
1349 #define E1000_82542_GSCL_3 E1000_GSCL_3
1350 #define E1000_82542_GSCL_4 E1000_GSCL_4
1351 #define E1000_82542_FACTPS E1000_FACTPS
1352 #define E1000_82542_SWSM E1000_SWSM
1353 #define E1000_82542_FWSM E1000_FWSM
1354 #define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1355 #define E1000_82542_IAC E1000_IAC
1356 #define E1000_82542_ICRXPTC E1000_ICRXPTC
1357 #define E1000_82542_ICRXATC E1000_ICRXATC
1358 #define E1000_82542_ICTXPTC E1000_ICTXPTC
1359 #define E1000_82542_ICTXATC E1000_ICTXATC
1360 #define E1000_82542_ICTXQEC E1000_ICTXQEC
1361 #define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1362 #define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1363 #define E1000_82542_ICRXOC E1000_ICRXOC
1364 #define E1000_82542_HICR E1000_HICR
1365 
1366 #define E1000_82542_CPUVEC E1000_CPUVEC
1367 #define E1000_82542_MRQC E1000_MRQC
1368 #define E1000_82542_RETA E1000_RETA
1369 #define E1000_82542_RSSRK E1000_RSSRK
1370 #define E1000_82542_RSSIM E1000_RSSIM
1371 #define E1000_82542_RSSIR E1000_RSSIR
1372 #define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
1373 #define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC
1374 
1375 /* Statistics counters collected by the MAC */
1376 struct e1000_hw_stats {
1377  uint64_t crcerrs;
1378  uint64_t algnerrc;
1379  uint64_t symerrs;
1380  uint64_t rxerrc;
1381  uint64_t mpc;
1382  uint64_t scc;
1383  uint64_t ecol;
1384  uint64_t mcc;
1385  uint64_t latecol;
1386  uint64_t colc;
1387  uint64_t dc;
1388  uint64_t tncrs;
1389  uint64_t sec;
1390  uint64_t cexterr;
1391  uint64_t rlec;
1392  uint64_t xonrxc;
1393  uint64_t xontxc;
1394  uint64_t xoffrxc;
1395  uint64_t xofftxc;
1396  uint64_t fcruc;
1397  uint64_t prc64;
1398  uint64_t prc127;
1399  uint64_t prc255;
1400  uint64_t prc511;
1401  uint64_t prc1023;
1402  uint64_t prc1522;
1403  uint64_t gprc;
1404  uint64_t bprc;
1405  uint64_t mprc;
1406  uint64_t gptc;
1407  uint64_t gorcl;
1408  uint64_t gorch;
1409  uint64_t gotcl;
1410  uint64_t gotch;
1411  uint64_t rnbc;
1412  uint64_t ruc;
1413  uint64_t rfc;
1414  uint64_t roc;
1415  uint64_t rjc;
1416  uint64_t mgprc;
1417  uint64_t mgpdc;
1418  uint64_t mgptc;
1419  uint64_t torl;
1420  uint64_t torh;
1421  uint64_t totl;
1422  uint64_t toth;
1423  uint64_t tpr;
1424  uint64_t tpt;
1425  uint64_t ptc64;
1426  uint64_t ptc127;
1427  uint64_t ptc255;
1428  uint64_t ptc511;
1429  uint64_t ptc1023;
1430  uint64_t ptc1522;
1431  uint64_t mptc;
1432  uint64_t bptc;
1433  uint64_t tsctc;
1434  uint64_t tsctfc;
1435  uint64_t iac;
1436  uint64_t icrxptc;
1437  uint64_t icrxatc;
1438  uint64_t ictxptc;
1439  uint64_t ictxatc;
1440  uint64_t ictxqec;
1441  uint64_t ictxqmtc;
1442  uint64_t icrxdmtc;
1443  uint64_t icrxoc;
1444 };
1445 
1446 /* Structure containing variables used by the shared code (e1000_hw.c) */
1447 struct e1000_hw {
1448  uint8_t *hw_addr;
1449  uint8_t *flash_address;
1450  e1000_mac_type mac_type;
1451  e1000_phy_type phy_type;
1452  uint32_t phy_init_script;
1453  e1000_media_type media_type;
1454  void *back;
1455  struct e1000_shadow_ram *eeprom_shadow_ram;
1456  uint32_t flash_bank_size;
1457  uint32_t flash_base_addr;
1458  e1000_fc_type fc;
1459  e1000_bus_speed bus_speed;
1460  e1000_bus_width bus_width;
1461  e1000_bus_type bus_type;
1462  struct e1000_eeprom_info eeprom;
1463  e1000_ms_type master_slave;
1464  e1000_ms_type original_master_slave;
1465  e1000_ffe_config ffe_config_state;
1466  uint32_t asf_firmware_present;
1467  uint32_t eeprom_semaphore_present;
1468  uint32_t swfw_sync_present;
1469  uint32_t swfwhw_semaphore_present;
1470  unsigned long io_base;
1471  uint32_t phy_id;
1472  uint32_t phy_revision;
1473  uint32_t phy_addr;
1474  uint32_t original_fc;
1475  uint32_t txcw;
1476  uint32_t autoneg_failed;
1477  uint32_t max_frame_size;
1478  uint32_t min_frame_size;
1479  uint32_t mc_filter_type;
1480  uint32_t num_mc_addrs;
1481  uint32_t collision_delta;
1482  uint32_t tx_packet_delta;
1483  uint32_t ledctl_default;
1484  uint32_t ledctl_mode1;
1485  uint32_t ledctl_mode2;
1486  boolean_t tx_pkt_filtering;
1487  struct e1000_host_mng_dhcp_cookie mng_cookie;
1488  uint16_t phy_spd_default;
1489  uint16_t autoneg_advertised;
1490  uint16_t pci_cmd_word;
1491  uint16_t fc_high_water;
1492  uint16_t fc_low_water;
1493  uint16_t fc_pause_time;
1494  uint16_t current_ifs_val;
1495  uint16_t ifs_min_val;
1496  uint16_t ifs_max_val;
1497  uint16_t ifs_step_size;
1498  uint16_t ifs_ratio;
1499  uint16_t device_id;
1500  uint16_t vendor_id;
1501  uint16_t subsystem_id;
1502  uint16_t subsystem_vendor_id;
1503  uint8_t revision_id;
1504  uint8_t autoneg;
1505  uint8_t mdix;
1506  uint8_t forced_speed_duplex;
1507  uint8_t wait_autoneg_complete;
1508  uint8_t dma_fairness;
1509  uint8_t mac_addr[NODE_ADDRESS_SIZE];
1510  uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
1511  boolean_t disable_polarity_correction;
1512  boolean_t speed_downgraded;
1513  e1000_smart_speed smart_speed;
1514  e1000_dsp_config dsp_config_state;
1515  boolean_t get_link_status;
1516  boolean_t serdes_link_down;
1517  boolean_t tbi_compatibility_en;
1518  boolean_t tbi_compatibility_on;
1519  boolean_t laa_is_present;
1520  boolean_t phy_reset_disable;
1521  boolean_t fc_send_xon;
1522  boolean_t fc_strict_ieee;
1523  boolean_t report_tx_early;
1524  boolean_t adaptive_ifs;
1525  boolean_t ifs_params_forced;
1526  boolean_t in_ifs_mode;
1527  boolean_t mng_reg_access_disabled;
1528  boolean_t leave_av_bit_off;
1529  boolean_t kmrn_lock_loss_workaround_disabled;
1530 };
1531 
1532 
1533 #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1534 #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1535 #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1536 #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1537 #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1538 #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1539 #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1540 #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1541 /* Register Bit Masks */
1542 /* Device Control */
1543 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1544 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1545 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1546 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1547 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1548 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1549 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1550 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1551 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1552 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1553 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1554 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1555 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1556 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1557 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1558 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1559 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1560 #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
1561 #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1562 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
1563 #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
1564 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1565 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1566 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1567 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1568 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1569 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1570 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1571 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1572 #define E1000_CTRL_RST 0x04000000 /* Global reset */
1573 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1574 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1575 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1576 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1577 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1578 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1579 
1580 /* Device Status */
1581 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1582 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1583 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1584 #define E1000_STATUS_FUNC_SHIFT 2
1585 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1586 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1587 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1588 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1589 #define E1000_STATUS_SPEED_MASK 0x000000C0
1590 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1591 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1592 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1593 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
1594  by EEPROM/Flash */
1595 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1596 #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1597 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1598 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1599 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1600 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1601 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1602 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1603 #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
1604 #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
1605 #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
1606 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
1607 #define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
1608 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
1609 #define E1000_STATUS_FUSE_8 0x04000000
1610 #define E1000_STATUS_FUSE_9 0x08000000
1611 #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
1612 #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
1613 
1614 /* Constants used to intrepret the masked PCI-X bus speed. */
1615 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1616 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1617 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1618 
1619 /* EEPROM/Flash Control */
1620 #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1621 #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1622 #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1623 #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1624 #define E1000_EECD_FWE_MASK 0x00000030
1625 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1626 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1627 #define E1000_EECD_FWE_SHIFT 4
1628 #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1629 #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1630 #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1631 #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1632 #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1633  * (0-small, 1-large) */
1634 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1635 #ifndef E1000_EEPROM_GRANT_ATTEMPTS
1636 #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1637 #endif
1638 #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1639 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1640 #define E1000_EECD_SIZE_EX_SHIFT 11
1641 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1642 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1643 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1644 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1645 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1646 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1647 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1648 #define E1000_EECD_SECVAL_SHIFT 22
1649 #define E1000_STM_OPCODE 0xDB00
1650 #define E1000_HICR_FW_RESET 0xC0
1651 
1652 #define E1000_SHADOW_RAM_WORDS 2048
1653 #define E1000_ICH8_NVM_SIG_WORD 0x13
1654 #define E1000_ICH8_NVM_SIG_MASK 0xC0
1655 
1656 /* EEPROM Read */
1657 #define E1000_EERD_START 0x00000001 /* Start Read */
1658 #define E1000_EERD_DONE 0x00000010 /* Read Done */
1659 #define E1000_EERD_ADDR_SHIFT 8
1660 #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1661 #define E1000_EERD_DATA_SHIFT 16
1662 #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1663 
1664 /* SPI EEPROM Status Register */
1665 #define EEPROM_STATUS_RDY_SPI 0x01
1666 #define EEPROM_STATUS_WEN_SPI 0x02
1667 #define EEPROM_STATUS_BP0_SPI 0x04
1668 #define EEPROM_STATUS_BP1_SPI 0x08
1669 #define EEPROM_STATUS_WPEN_SPI 0x80
1670 
1671 /* Extended Device Control */
1672 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1673 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1674 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1675 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1676 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1677 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1678 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1679 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1680 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1681 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1682 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1683 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1684 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1685 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1686 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1687 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1688 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1689 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1690 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1691 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1692 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1693 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1694 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
1695 #define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000
1696 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1697 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1698 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1699 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1700 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1701 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1702 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1703 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1704 #define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
1705 #define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
1706 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
1707 
1708 /* MDI Control */
1709 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1710 #define E1000_MDIC_REG_MASK 0x001F0000
1711 #define E1000_MDIC_REG_SHIFT 16
1712 #define E1000_MDIC_PHY_MASK 0x03E00000
1713 #define E1000_MDIC_PHY_SHIFT 21
1714 #define E1000_MDIC_OP_WRITE 0x04000000
1715 #define E1000_MDIC_OP_READ 0x08000000
1716 #define E1000_MDIC_READY 0x10000000
1717 #define E1000_MDIC_INT_EN 0x20000000
1718 #define E1000_MDIC_ERROR 0x40000000
1719 
1720 #define E1000_KUMCTRLSTA_MASK 0x0000FFFF
1721 #define E1000_KUMCTRLSTA_OFFSET 0x001F0000
1722 #define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
1723 #define E1000_KUMCTRLSTA_REN 0x00200000
1724 
1725 #define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
1726 #define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
1727 #define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
1728 #define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
1729 #define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
1730 #define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
1731 #define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
1732 #define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
1733 #define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
1734 
1735 /* FIFO Control */
1736 #define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
1737 #define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1738 
1739 /* In-Band Control */
1740 #define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
1741 #define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1742 
1743 /* Half-Duplex Control */
1744 #define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1745 #define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1746 
1747 #define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
1748 
1749 #define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
1750 #define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
1751 
1752 #define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
1753 #define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
1754 #define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
1755 
1756 #define E1000_KABGTXD_BGSQLBIAS 0x00050000
1757 
1758 #define E1000_PHY_CTRL_SPD_EN 0x00000001
1759 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1760 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1761 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1762 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1763 #define E1000_PHY_CTRL_B2B_EN 0x00000080
1764 
1765 /* LED Control */
1766 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1767 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
1768 #define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
1769 #define E1000_LEDCTL_LED0_IVRT 0x00000040
1770 #define E1000_LEDCTL_LED0_BLINK 0x00000080
1771 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1772 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
1773 #define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
1774 #define E1000_LEDCTL_LED1_IVRT 0x00004000
1775 #define E1000_LEDCTL_LED1_BLINK 0x00008000
1776 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1777 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
1778 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
1779 #define E1000_LEDCTL_LED2_IVRT 0x00400000
1780 #define E1000_LEDCTL_LED2_BLINK 0x00800000
1781 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1782 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
1783 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
1784 #define E1000_LEDCTL_LED3_IVRT 0x40000000
1785 #define E1000_LEDCTL_LED3_BLINK 0x80000000
1786 
1787 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1788 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1789 #define E1000_LEDCTL_MODE_LINK_UP 0x2
1790 #define E1000_LEDCTL_MODE_ACTIVITY 0x3
1791 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1792 #define E1000_LEDCTL_MODE_LINK_10 0x5
1793 #define E1000_LEDCTL_MODE_LINK_100 0x6
1794 #define E1000_LEDCTL_MODE_LINK_1000 0x7
1795 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1796 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1797 #define E1000_LEDCTL_MODE_COLLISION 0xA
1798 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1799 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1800 #define E1000_LEDCTL_MODE_PAUSED 0xD
1801 #define E1000_LEDCTL_MODE_LED_ON 0xE
1802 #define E1000_LEDCTL_MODE_LED_OFF 0xF
1803 
1804 /* Receive Address */
1805 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1806 
1807 /* Interrupt Cause Read */
1808 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1809 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1810 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1811 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1812 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1813 #define E1000_ICR_RXO 0x00000040 /* rx overrun */
1814 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1815 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1816 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1817 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1818 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1819 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1820 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1821 #define E1000_ICR_TXD_LOW 0x00008000
1822 #define E1000_ICR_SRPD 0x00010000
1823 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1824 #define E1000_ICR_MNG 0x00040000 /* Manageability event */
1825 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1826 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1827 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
1828 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
1829 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
1830 #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
1831 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1832 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1833 #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
1834 #define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
1835 #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
1836 #define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
1837 
1838 /* Interrupt Cause Set */
1839 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1840 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1841 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1842 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1843 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1844 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1845 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1846 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1847 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1848 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1849 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1850 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1851 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1852 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1853 #define E1000_ICS_SRPD E1000_ICR_SRPD
1854 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1855 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1856 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1857 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1858 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1859 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1860 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1861 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1862 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1863 #define E1000_ICS_DSW E1000_ICR_DSW
1864 #define E1000_ICS_PHYINT E1000_ICR_PHYINT
1865 #define E1000_ICS_EPRST E1000_ICR_EPRST
1866 
1867 /* Interrupt Mask Set */
1868 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1869 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1870 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1871 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1872 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1873 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1874 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1875 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1876 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1877 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1878 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1879 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1880 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1881 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1882 #define E1000_IMS_SRPD E1000_ICR_SRPD
1883 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1884 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1885 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1886 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1887 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1888 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1889 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1890 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1891 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1892 #define E1000_IMS_DSW E1000_ICR_DSW
1893 #define E1000_IMS_PHYINT E1000_ICR_PHYINT
1894 #define E1000_IMS_EPRST E1000_ICR_EPRST
1895 
1896 /* Interrupt Mask Clear */
1897 #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1898 #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1899 #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1900 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1901 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1902 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1903 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1904 #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1905 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1906 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1907 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1908 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1909 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1910 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1911 #define E1000_IMC_SRPD E1000_ICR_SRPD
1912 #define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1913 #define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1914 #define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
1915 #define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1916 #define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1917 #define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1918 #define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1919 #define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1920 #define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1921 #define E1000_IMC_DSW E1000_ICR_DSW
1922 #define E1000_IMC_PHYINT E1000_ICR_PHYINT
1923 #define E1000_IMC_EPRST E1000_ICR_EPRST
1924 
1925 /* Receive Control */
1926 #define E1000_RCTL_RST 0x00000001 /* Software reset */
1927 #define E1000_RCTL_EN 0x00000002 /* enable */
1928 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1929 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1930 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1931 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1932 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1933 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1934 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1935 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1936 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1937 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1938 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1939 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1940 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1941 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1942 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1943 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1944 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1945 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1946 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1947 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1948 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1949 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1950 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1951 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1952 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1953 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1954 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1955 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1956 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1957 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1958 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1959 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1960 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1961 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1962 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1963 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1964 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1965 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1966 
1967 /* Use byte values for the following shift parameters
1968  * Usage:
1969  * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1970  * E1000_PSRCTL_BSIZE0_MASK) |
1971  * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1972  * E1000_PSRCTL_BSIZE1_MASK) |
1973  * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1974  * E1000_PSRCTL_BSIZE2_MASK) |
1975  * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1976  * E1000_PSRCTL_BSIZE3_MASK))
1977  * where value0 = [128..16256], default=256
1978  * value1 = [1024..64512], default=4096
1979  * value2 = [0..64512], default=4096
1980  * value3 = [0..64512], default=0
1981  */
1982 
1983 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1984 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1985 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1986 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1987 
1988 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1989 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1990 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1991 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1992 
1993 /* SW_W_SYNC definitions */
1994 #define E1000_SWFW_EEP_SM 0x0001
1995 #define E1000_SWFW_PHY0_SM 0x0002
1996 #define E1000_SWFW_PHY1_SM 0x0004
1997 #define E1000_SWFW_MAC_CSR_SM 0x0008
1998 
1999 /* Receive Descriptor */
2000 #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
2001 #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
2002 #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
2003 #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
2004 #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
2005 
2006 /* Flow Control */
2007 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
2008 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
2009 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
2010 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
2011 
2012 /* Header split receive */
2013 #define E1000_RFCTL_ISCSI_DIS 0x00000001
2014 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
2015 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1
2016 #define E1000_RFCTL_NFSW_DIS 0x00000040
2017 #define E1000_RFCTL_NFSR_DIS 0x00000080
2018 #define E1000_RFCTL_NFS_VER_MASK 0x00000300
2019 #define E1000_RFCTL_NFS_VER_SHIFT 8
2020 #define E1000_RFCTL_IPV6_DIS 0x00000400
2021 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
2022 #define E1000_RFCTL_ACK_DIS 0x00001000
2023 #define E1000_RFCTL_ACKD_DIS 0x00002000
2024 #define E1000_RFCTL_IPFRSP_DIS 0x00004000
2025 #define E1000_RFCTL_EXTEN 0x00008000
2026 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
2027 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
2028 
2029 /* Receive Descriptor Control */
2030 #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
2031 #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
2032 #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
2033 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
2034 
2035 /* Transmit Descriptor Control */
2036 #define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
2037 #define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
2038 #define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
2039 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
2040 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
2041 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
2042 #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
2043  still to be processed. */
2044 /* Transmit Configuration Word */
2045 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
2046 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
2047 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
2048 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
2049 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
2050 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
2051 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */
2052 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
2053 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
2054 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
2055 
2056 /* Receive Configuration Word */
2057 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
2058 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
2059 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
2060 #define E1000_RXCW_CC 0x10000000 /* Receive config change */
2061 #define E1000_RXCW_C 0x20000000 /* Receive config */
2062 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
2063 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
2064 
2065 /* Transmit Control */
2066 #define E1000_TCTL_RST 0x00000001 /* software reset */
2067 #define E1000_TCTL_EN 0x00000002 /* enable tx */
2068 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */
2069 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
2070 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
2071 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
2072 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
2073 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
2074 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
2075 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
2076 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
2077 /* Extended Transmit Control */
2078 #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
2079 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
2080 
2081 #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
2082 
2083 /* Receive Checksum Control */
2084 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
2085 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
2086 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
2087 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
2088 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
2089 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
2090 
2091 /* Multiple Receive Queue Control */
2092 #define E1000_MRQC_ENABLE_MASK 0x00000003
2093 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
2094 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004
2095 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
2096 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
2097 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
2098 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
2099 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
2100 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
2101 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
2102 
2103 /* Definitions for power management and wakeup registers */
2104 /* Wake Up Control */
2105 #define E1000_WUC_APME 0x00000001 /* APM Enable */
2106 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
2107 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
2108 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
2109 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */
2110 
2111 /* Wake Up Filter Control */
2112 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
2113 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
2114 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
2115 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
2116 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
2117 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
2118 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
2119 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
2120 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
2121 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
2122 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
2123 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
2124 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
2125 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
2126 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
2127 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
2128 
2129 /* Wake Up Status */
2130 #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
2131 #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
2132 #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
2133 #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
2134 #define E1000_WUS_BC 0x00000010 /* Broadcast Received */
2135 #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
2136 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
2137 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
2138 #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
2139 #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
2140 #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
2141 #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
2142 #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
2143 
2144 /* Management Control */
2145 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
2146 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
2147 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
2148 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
2149 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
2150 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
2151 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
2152 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
2153 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
2154 #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
2155  * Filtering */
2156 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
2157 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
2158 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
2159 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
2160 #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
2161 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
2162 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
2163  * filtering */
2164 #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
2165  * memory */
2166 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
2167  * filtering */
2168 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
2169 #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
2170 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
2171 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
2172 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
2173 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
2174 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
2175 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
2176 
2177 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
2178 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
2179 
2180 /* SW Semaphore Register */
2181 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2182 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2183 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2184 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
2185 
2186 /* FW Semaphore Register */
2187 #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
2188 #define E1000_FWSM_MODE_SHIFT 1
2189 #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2190 
2191 #define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2192 #define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2193 #define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2194 #define E1000_FWSM_SKUEL_SHIFT 29
2195 #define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2196 #define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2197 #define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2198 #define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2199 
2200 /* FFLT Debug Register */
2201 #define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2202 
2203 typedef enum {
2204  e1000_mng_mode_none = 0,
2205  e1000_mng_mode_asf,
2206  e1000_mng_mode_pt,
2207  e1000_mng_mode_ipmi,
2208  e1000_mng_mode_host_interface_only
2209 } e1000_mng_mode;
2210 
2211 /* Host Inteface Control Register */
2212 #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
2213 #define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
2214  * to put command in RAM */
2215 #define E1000_HICR_SV 0x00000004 /* Status Validity */
2216 #define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
2217 
2218 /* Host Interface Command Interface - Address range 0x8800-0x8EFF */
2219 #define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
2220 #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
2221 #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
2222 #define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
2223 
2224 struct e1000_host_command_header {
2225  uint8_t command_id;
2226  uint8_t command_length;
2227  uint8_t command_options; /* I/F bits for command, status for return */
2228  uint8_t checksum;
2229 };
2230 struct e1000_host_command_info {
2231  struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
2232  uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
2233 };
2234 
2235 /* Host SMB register #0 */
2236 #define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
2237 #define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
2238 #define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
2239 #define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
2240 
2241 /* Host SMB register #1 */
2242 #define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
2243 #define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
2244 #define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
2245 #define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
2246 
2247 /* FW Status Register */
2248 #define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
2249 
2250 /* Wake Up Packet Length */
2251 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
2252 
2253 #define E1000_MDALIGN 4096
2254 
2255 /* PCI-Ex registers*/
2256 
2257 /* PCI-Ex Control Register */
2258 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
2259 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
2260 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
2261 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
2262 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
2263 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
2264 
2265 #define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
2266  E1000_GCR_RXDSCW_NO_SNOOP | \
2267  E1000_GCR_RXDSCR_NO_SNOOP | \
2268  E1000_GCR_TXD_NO_SNOOP | \
2269  E1000_GCR_TXDSCW_NO_SNOOP | \
2270  E1000_GCR_TXDSCR_NO_SNOOP)
2271 
2272 #define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2273 
2274 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2275 /* Function Active and Power State to MNG */
2276 #define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
2277 #define E1000_FACTPS_LAN0_VALID 0x00000004
2278 #define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
2279 #define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
2280 #define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
2281 #define E1000_FACTPS_LAN1_VALID 0x00000100
2282 #define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
2283 #define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
2284 #define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
2285 #define E1000_FACTPS_IDE_ENABLE 0x00004000
2286 #define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
2287 #define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
2288 #define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
2289 #define E1000_FACTPS_SP_ENABLE 0x00100000
2290 #define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
2291 #define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
2292 #define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
2293 #define E1000_FACTPS_IPMI_ENABLE 0x04000000
2294 #define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
2295 #define E1000_FACTPS_MNGCG 0x20000000
2296 #define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
2297 #define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
2298 
2299 /* EEPROM Commands - Microwire */
2300 #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
2301 #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
2302 #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
2303 #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
2304 #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
2305 
2306 /* EEPROM Commands - SPI */
2307 #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2308 #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2309 #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2310 #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
2311 #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
2312 #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
2313 #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
2314 #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
2315 #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2316 #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2317 #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
2318 
2319 /* EEPROM Size definitions */
2320 #define EEPROM_WORD_SIZE_SHIFT 6
2321 #define EEPROM_SIZE_SHIFT 10
2322 #define EEPROM_SIZE_MASK 0x1C00
2323 
2324 /* EEPROM Word Offsets */
2325 #define EEPROM_COMPAT 0x0003
2326 #define EEPROM_ID_LED_SETTINGS 0x0004
2327 #define EEPROM_VERSION 0x0005
2328 #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
2329 #define EEPROM_PHY_CLASS_WORD 0x0007
2330 #define EEPROM_INIT_CONTROL1_REG 0x000A
2331 #define EEPROM_INIT_CONTROL2_REG 0x000F
2332 #define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
2333 #define EEPROM_INIT_CONTROL3_PORT_B 0x0014
2334 #define EEPROM_INIT_3GIO_3 0x001A
2335 #define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
2336 #define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2337 #define EEPROM_CFG 0x0012
2338 #define EEPROM_FLASH_VERSION 0x0032
2339 #define EEPROM_CHECKSUM_REG 0x003F
2340 
2341 #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
2342 #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
2343 
2344 /* Word definitions for ID LED Settings */
2345 #define ID_LED_RESERVED_0000 0x0000
2346 #define ID_LED_RESERVED_FFFF 0xFFFF
2347 #define ID_LED_RESERVED_82573 0xF746
2348 #define ID_LED_DEFAULT_82573 0x1811
2349 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2350  (ID_LED_OFF1_OFF2 << 8) | \
2351  (ID_LED_DEF1_DEF2 << 4) | \
2352  (ID_LED_DEF1_DEF2))
2353 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
2354  (ID_LED_DEF1_OFF2 << 8) | \
2355  (ID_LED_DEF1_ON2 << 4) | \
2356  (ID_LED_DEF1_DEF2))
2357 #define ID_LED_DEF1_DEF2 0x1
2358 #define ID_LED_DEF1_ON2 0x2
2359 #define ID_LED_DEF1_OFF2 0x3
2360 #define ID_LED_ON1_DEF2 0x4
2361 #define ID_LED_ON1_ON2 0x5
2362 #define ID_LED_ON1_OFF2 0x6
2363 #define ID_LED_OFF1_DEF2 0x7
2364 #define ID_LED_OFF1_ON2 0x8
2365 #define ID_LED_OFF1_OFF2 0x9
2366 
2367 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2368 #define IGP_ACTIVITY_LED_ENABLE 0x0300
2369 #define IGP_LED3_MODE 0x07000000
2370 
2371 
2372 /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2373 #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2374 
2375 /* Mask bit for PHY class in Word 7 of the EEPROM */
2376 #define EEPROM_PHY_CLASS_A 0x8000
2377 
2378 /* Mask bits for fields in Word 0x0a of the EEPROM */
2379 #define EEPROM_WORD0A_ILOS 0x0010
2380 #define EEPROM_WORD0A_SWDPIO 0x01E0
2381 #define EEPROM_WORD0A_LRST 0x0200
2382 #define EEPROM_WORD0A_FD 0x0400
2383 #define EEPROM_WORD0A_66MHZ 0x0800
2384 
2385 /* Mask bits for fields in Word 0x0f of the EEPROM */
2386 #define EEPROM_WORD0F_PAUSE_MASK 0x3000
2387 #define EEPROM_WORD0F_PAUSE 0x1000
2388 #define EEPROM_WORD0F_ASM_DIR 0x2000
2389 #define EEPROM_WORD0F_ANE 0x0800
2390 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2391 #define EEPROM_WORD0F_LPLU 0x0001
2392 
2393 /* Mask bits for fields in Word 0x10/0x20 of the EEPROM */
2394 #define EEPROM_WORD1020_GIGA_DISABLE 0x0010
2395 #define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008
2396 
2397 /* Mask bits for fields in Word 0x1a of the EEPROM */
2398 #define EEPROM_WORD1A_ASPM_MASK 0x000C
2399 
2400 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
2401 #define EEPROM_SUM 0xBABA
2402 
2403 /* EEPROM Map defines (WORD OFFSETS)*/
2404 #define EEPROM_NODE_ADDRESS_BYTE_0 0
2405 #define EEPROM_PBA_BYTE_1 8
2406 
2407 #define EEPROM_RESERVED_WORD 0xFFFF
2408 
2409 /* EEPROM Map Sizes (Byte Counts) */
2410 #define PBA_SIZE 4
2411 
2412 /* Collision related configuration parameters */
2413 #define E1000_COLLISION_THRESHOLD 15
2414 #define E1000_CT_SHIFT 4
2415 /* Collision distance is a 0-based value that applies to
2416  * half-duplex-capable hardware only. */
2417 #define E1000_COLLISION_DISTANCE 63
2418 #define E1000_COLLISION_DISTANCE_82542 64
2419 #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2420 #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2421 #define E1000_COLD_SHIFT 12
2422 
2423 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2424 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
2425 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
2426 
2427 /* Default values for the transmit IPG register */
2428 #define DEFAULT_82542_TIPG_IPGT 10
2429 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
2430 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
2431 
2432 #define E1000_TIPG_IPGT_MASK 0x000003FF
2433 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
2434 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
2435 
2436 #define DEFAULT_82542_TIPG_IPGR1 2
2437 #define DEFAULT_82543_TIPG_IPGR1 8
2438 #define E1000_TIPG_IPGR1_SHIFT 10
2439 
2440 #define DEFAULT_82542_TIPG_IPGR2 10
2441 #define DEFAULT_82543_TIPG_IPGR2 6
2442 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
2443 #define E1000_TIPG_IPGR2_SHIFT 20
2444 
2445 #define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
2446 #define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
2447 #define E1000_TXDMAC_DPP 0x00000001
2448 
2449 /* Adaptive IFS defines */
2450 #define TX_THRESHOLD_START 8
2451 #define TX_THRESHOLD_INCREMENT 10
2452 #define TX_THRESHOLD_DECREMENT 1
2453 #define TX_THRESHOLD_STOP 190
2454 #define TX_THRESHOLD_DISABLE 0
2455 #define TX_THRESHOLD_TIMER_MS 10000
2456 #define MIN_NUM_XMITS 1000
2457 #define IFS_MAX 80
2458 #define IFS_STEP 10
2459 #define IFS_MIN 40
2460 #define IFS_RATIO 4
2461 
2462 /* Extended Configuration Control and Size */
2463 #define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2464 #define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2465 #define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2466 #define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2467 #define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2468 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2469 #define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2470 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000
2471 
2472 #define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2473 #define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2474 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2475 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
2476 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2477 
2478 /* PBA constants */
2479 #define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2480 #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2481 #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2482 #define E1000_PBA_22K 0x0016
2483 #define E1000_PBA_24K 0x0018
2484 #define E1000_PBA_30K 0x001E
2485 #define E1000_PBA_32K 0x0020
2486 #define E1000_PBA_34K 0x0022
2487 #define E1000_PBA_38K 0x0026
2488 #define E1000_PBA_40K 0x0028
2489 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2490 
2491 #define E1000_PBS_16K E1000_PBA_16K
2492 
2493 /* Flow Control Constants */
2494 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2495 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
2496 #define FLOW_CONTROL_TYPE 0x8808
2497 
2498 /* The historical defaults for the flow control values are given below. */
2499 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2500 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2501 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
2502 
2503 /* PCIX Config space */
2504 #define PCIX_COMMAND_REGISTER 0xE6
2505 #define PCIX_STATUS_REGISTER_LO 0xE8
2506 #define PCIX_STATUS_REGISTER_HI 0xEA
2507 
2508 #define PCIX_COMMAND_MMRBC_MASK 0x000C
2509 #define PCIX_COMMAND_MMRBC_SHIFT 0x2
2510 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060
2511 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
2512 #define PCIX_STATUS_HI_MMRBC_4K 0x3
2513 #define PCIX_STATUS_HI_MMRBC_2K 0x2
2514 
2515 
2516 /* Number of bits required to shift right the "pause" bits from the
2517  * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2518  */
2519 #define PAUSE_SHIFT 5
2520 
2521 /* Number of bits required to shift left the "SWDPIO" bits from the
2522  * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
2523  */
2524 #define SWDPIO_SHIFT 17
2525 
2526 /* Number of bits required to shift left the "SWDPIO_EXT" bits from the
2527  * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
2528  */
2529 #define SWDPIO__EXT_SHIFT 4
2530 
2531 /* Number of bits required to shift left the "ILOS" bit from the EEPROM
2532  * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
2533  */
2534 #define ILOS_SHIFT 3
2535 
2536 
2537 #define RECEIVE_BUFFER_ALIGN_SIZE (256)
2538 
2539 /* Number of milliseconds we wait for auto-negotiation to complete */
2540 #define LINK_UP_TIMEOUT 500
2541 
2542 /* Number of 100 microseconds we wait for PCI Express master disable */
2543 #define MASTER_DISABLE_TIMEOUT 800
2544 /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2545 #define AUTO_READ_DONE_TIMEOUT 10
2546 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
2547 #define PHY_CFG_TIMEOUT 100
2548 
2549 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
2550 
2551 /* The carrier extension symbol, as received by the NIC. */
2552 #define CARRIER_EXTENSION 0x0F
2553 
2554 /* TBI_ACCEPT macro definition:
2555  *
2556  * This macro requires:
2557  * adapter = a pointer to struct e1000_hw
2558  * status = the 8 bit status field of the RX descriptor with EOP set
2559  * error = the 8 bit error field of the RX descriptor with EOP set
2560  * length = the sum of all the length fields of the RX descriptors that
2561  * make up the current frame
2562  * last_byte = the last byte of the frame DMAed by the hardware
2563  * max_frame_length = the maximum frame length we want to accept.
2564  * min_frame_length = the minimum frame length we want to accept.
2565  *
2566  * This macro is a conditional that should be used in the interrupt
2567  * handler's Rx processing routine when RxErrors have been detected.
2568  *
2569  * Typical use:
2570  * ...
2571  * if (TBI_ACCEPT) {
2572  * accept_frame = TRUE;
2573  * e1000_tbi_adjust_stats(adapter, MacAddress);
2574  * frame_length--;
2575  * } else {
2576  * accept_frame = FALSE;
2577  * }
2578  * ...
2579  */
2580 
2581 #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
2582  ((adapter)->tbi_compatibility_on && \
2583  (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
2584  ((last_byte) == CARRIER_EXTENSION) && \
2585  (((status) & E1000_RXD_STAT_VP) ? \
2586  (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2587  ((length) <= ((adapter)->max_frame_size + 1))) : \
2588  (((length) > (adapter)->min_frame_size) && \
2589  ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2590 
2591 
2592 /* Structures, enums, and macros for the PHY */
2593 
2594 /* Bit definitions for the Management Data IO (MDIO) and Management Data
2595  * Clock (MDC) pins in the Device Control Register.
2596  */
2597 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
2598 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
2599 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
2600 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
2601 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
2602 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
2603 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
2604 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
2605 
2606 /* PHY 1000 MII Register/Bit Definitions */
2607 /* PHY Registers defined by IEEE */
2608 #define PHY_CTRL 0x00 /* Control Register */
2609 #define PHY_STATUS 0x01 /* Status Regiser */
2610 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2611 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2612 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2613 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2614 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2615 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2616 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2617 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2618 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2619 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2620 
2621 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2622 #define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
2623 
2624 /* M88E1000 Specific Registers */
2625 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2626 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2627 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2628 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2629 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2630 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2631 
2632 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2633 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2634 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2635 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2636 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
2637 
2638 #define IGP01E1000_IEEE_REGS_PAGE 0x0000
2639 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2640 #define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2641 
2642 /* IGP01E1000 Specific Registers */
2643 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2644 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2645 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2646 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2647 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2648 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2649 #define IGP02E1000_PHY_POWER_MGMT 0x19
2650 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
2651 
2652 /* IGP01E1000 AGC Registers - stores the cable length values*/
2653 #define IGP01E1000_PHY_AGC_A 0x1172
2654 #define IGP01E1000_PHY_AGC_B 0x1272
2655 #define IGP01E1000_PHY_AGC_C 0x1472
2656 #define IGP01E1000_PHY_AGC_D 0x1872
2657 
2658 /* IGP02E1000 AGC Registers for cable length values */
2659 #define IGP02E1000_PHY_AGC_A 0x11B1
2660 #define IGP02E1000_PHY_AGC_B 0x12B1
2661 #define IGP02E1000_PHY_AGC_C 0x14B1
2662 #define IGP02E1000_PHY_AGC_D 0x18B1
2663 
2664 /* IGP01E1000 DSP Reset Register */
2665 #define IGP01E1000_PHY_DSP_RESET 0x1F33
2666 #define IGP01E1000_PHY_DSP_SET 0x1F71
2667 #define IGP01E1000_PHY_DSP_FFE 0x1F35
2668 
2669 #define IGP01E1000_PHY_CHANNEL_NUM 4
2670 #define IGP02E1000_PHY_CHANNEL_NUM 4
2671 
2672 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171
2673 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271
2674 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471
2675 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871
2676 
2677 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
2678 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
2679 
2680 #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
2681 #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
2682 #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
2683 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
2684 
2685 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
2686 /* IGP01E1000 PCS Initialization register - stores the polarity status when
2687  * speed = 1000 Mbps. */
2688 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
2689 #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
2690 
2691 #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2692 
2693 /* Bits...
2694  * 15-5: page
2695  * 4-0: register offset
2696  */
2697 #define GG82563_PAGE_SHIFT 5
2698 #define GG82563_REG(page, reg) \
2699  (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2700 #define GG82563_MIN_ALT_REG 30
2701 
2702 /* GG82563 Specific Registers */
2703 #define GG82563_PHY_SPEC_CTRL \
2704  GG82563_REG(0, 16) /* PHY Specific Control */
2705 #define GG82563_PHY_SPEC_STATUS \
2706  GG82563_REG(0, 17) /* PHY Specific Status */
2707 #define GG82563_PHY_INT_ENABLE \
2708  GG82563_REG(0, 18) /* Interrupt Enable */
2709 #define GG82563_PHY_SPEC_STATUS_2 \
2710  GG82563_REG(0, 19) /* PHY Specific Status 2 */
2711 #define GG82563_PHY_RX_ERR_CNTR \
2712  GG82563_REG(0, 21) /* Receive Error Counter */
2713 #define GG82563_PHY_PAGE_SELECT \
2714  GG82563_REG(0, 22) /* Page Select */
2715 #define GG82563_PHY_SPEC_CTRL_2 \
2716  GG82563_REG(0, 26) /* PHY Specific Control 2 */
2717 #define GG82563_PHY_PAGE_SELECT_ALT \
2718  GG82563_REG(0, 29) /* Alternate Page Select */
2719 #define GG82563_PHY_TEST_CLK_CTRL \
2720  GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
2721 
2722 #define GG82563_PHY_MAC_SPEC_CTRL \
2723  GG82563_REG(2, 21) /* MAC Specific Control Register */
2724 #define GG82563_PHY_MAC_SPEC_CTRL_2 \
2725  GG82563_REG(2, 26) /* MAC Specific Control 2 */
2726 
2727 #define GG82563_PHY_DSP_DISTANCE \
2728  GG82563_REG(5, 26) /* DSP Distance */
2729 
2730 /* Page 193 - Port Control Registers */
2731 #define GG82563_PHY_KMRN_MODE_CTRL \
2732  GG82563_REG(193, 16) /* Kumeran Mode Control */
2733 #define GG82563_PHY_PORT_RESET \
2734  GG82563_REG(193, 17) /* Port Reset */
2735 #define GG82563_PHY_REVISION_ID \
2736  GG82563_REG(193, 18) /* Revision ID */
2737 #define GG82563_PHY_DEVICE_ID \
2738  GG82563_REG(193, 19) /* Device ID */
2739 #define GG82563_PHY_PWR_MGMT_CTRL \
2740  GG82563_REG(193, 20) /* Power Management Control */
2741 #define GG82563_PHY_RATE_ADAPT_CTRL \
2742  GG82563_REG(193, 25) /* Rate Adaptation Control */
2743 
2744 /* Page 194 - KMRN Registers */
2745 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
2746  GG82563_REG(194, 16) /* FIFO's Control/Status */
2747 #define GG82563_PHY_KMRN_CTRL \
2748  GG82563_REG(194, 17) /* Control */
2749 #define GG82563_PHY_INBAND_CTRL \
2750  GG82563_REG(194, 18) /* Inband Control */
2751 #define GG82563_PHY_KMRN_DIAGNOSTIC \
2752  GG82563_REG(194, 19) /* Diagnostic */
2753 #define GG82563_PHY_ACK_TIMEOUTS \
2754  GG82563_REG(194, 20) /* Acknowledge Timeouts */
2755 #define GG82563_PHY_ADV_ABILITY \
2756  GG82563_REG(194, 21) /* Advertised Ability */
2757 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
2758  GG82563_REG(194, 23) /* Link Partner Advertised Ability */
2759 #define GG82563_PHY_ADV_NEXT_PAGE \
2760  GG82563_REG(194, 24) /* Advertised Next Page */
2761 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
2762  GG82563_REG(194, 25) /* Link Partner Advertised Next page */
2763 #define GG82563_PHY_KMRN_MISC \
2764  GG82563_REG(194, 26) /* Misc. */
2765 
2766 /* PHY Control Register */
2767 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2768 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2769 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2770 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2771 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2772 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
2773 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2774 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2775 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2776 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2777 
2778 /* PHY Status Register */
2779 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2780 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2781 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2782 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2783 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2784 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2785 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2786 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2787 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2788 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2789 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2790 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2791 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2792 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2793 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2794 
2795 /* Autoneg Advertisement Register */
2796 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2797 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2798 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2799 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2800 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2801 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2802 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2803 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2804 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2805 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2806 
2807 /* Link Partner Ability Register (Base Page) */
2808 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2809 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2810 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2811 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2812 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2813 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2814 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2815 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2816 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2817 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2818 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2819 
2820 /* Autoneg Expansion Register */
2821 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2822 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2823 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2824 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2825 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
2826 
2827 /* Next Page TX Register */
2828 #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2829 #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2830  * of different NP
2831  */
2832 #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2833  * 0 = cannot comply with msg
2834  */
2835 #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2836 #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2837  * 0 = sending last NP
2838  */
2839 
2840 /* Link Partner Next Page Register */
2841 #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2842 #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2843  * of different NP
2844  */
2845 #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2846  * 0 = cannot comply with msg
2847  */
2848 #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2849 #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2850 #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2851  * 0 = sending last NP
2852  */
2853 
2854 /* 1000BASE-T Control Register */
2855 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2856 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2857 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2858 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2859  /* 0=DTE device */
2860 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2861  /* 0=Configure PHY as Slave */
2862 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2863  /* 0=Automatic Master/Slave config */
2864 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2865 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2866 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2867 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2868 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2869 
2870 /* 1000BASE-T Status Register */
2871 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2872 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2873 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2874 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2875 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2876 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2877 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2878 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2879 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2880 #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2881 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
2882 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
2883 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2884 
2885 /* Extended Status Register */
2886 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2887 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2888 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2889 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2890 
2891 #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2892 #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2893 
2894 #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2895  /* (0=enable, 1=disable) */
2896 
2897 /* M88E1000 PHY Specific Control Register */
2898 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2899 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2900 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2901 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2902  * 0=CLK125 toggling
2903  */
2904 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2905  /* Manual MDI configuration */
2906 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2907 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2908  * 100BASE-TX/10BASE-T:
2909  * MDI Mode
2910  */
2911 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2912  * all speeds.
2913  */
2914 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2915  /* 1=Enable Extended 10BASE-T distance
2916  * (Lower 10BASE-T RX Threshold)
2917  * 0=Normal 10BASE-T RX Threshold */
2918 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2919  /* 1=5-Bit interface in 100BASE-TX
2920  * 0=MII interface in 100BASE-TX */
2921 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2922 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2923 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2924 
2925 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2926 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2927 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2928 
2929 /* M88E1000 PHY Specific Status Register */
2930 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2931 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2932 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2933 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2934 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2935  * 3=110-140M;4=>140M */
2936 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2937 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2938 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2939 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2940 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2941 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2942 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2943 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2944 
2945 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2946 #define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
2947 #define M88E1000_PSSR_MDIX_SHIFT 6
2948 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2949 
2950 /* M88E1000 Extended PHY Specific Control Register */
2951 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2952 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2953  * Will assert lost lock and bring
2954  * link down if idle not seen
2955  * within 1ms in 1000BASE-T
2956  */
2957 /* Number of times we will attempt to autonegotiate before downshifting if we
2958  * are the master */
2959 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2960 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2961 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2962 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2963 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2964 /* Number of times we will attempt to autonegotiate before downshifting if we
2965  * are the slave */
2966 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2967 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2968 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2969 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2970 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2971 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2972 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2973 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2974 
2975 /* M88EC018 Rev 2 specific DownShift settings */
2976 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
2977 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
2978 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
2979 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
2980 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
2981 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
2982 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
2983 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
2984 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
2985 
2986 /* IGP01E1000 Specific Port Config Register - R/W */
2987 #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2988 #define IGP01E1000_PSCFR_PRE_EN 0x0020
2989 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2990 #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2991 #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2992 #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2993 
2994 /* IGP01E1000 Specific Port Status Register - R/O */
2995 #define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2996 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2997 #define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2998 #define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2999 #define IGP01E1000_PSSR_LINK_UP 0x0400
3000 #define IGP01E1000_PSSR_MDIX 0x0800
3001 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
3002 #define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
3003 #define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
3004 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
3005 #define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
3006 #define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
3007 
3008 /* IGP01E1000 Specific Port Control Register - R/W */
3009 #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
3010 #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
3011 #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
3012 #define IGP01E1000_PSCR_FLIP_CHIP 0x0800
3013 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
3014 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
3015 
3016 /* IGP01E1000 Specific Port Link Health Register */
3017 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
3018 #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
3019 #define IGP01E1000_PLHR_MASTER_FAULT 0x2000
3020 #define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
3021 #define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
3022 #define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
3023 #define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
3024 #define IGP01E1000_PLHR_DATA_ERR_0 0x0100
3025 #define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
3026 #define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
3027 #define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
3028 #define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
3029 #define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
3030 #define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
3031 
3032 /* IGP01E1000 Channel Quality Register */
3033 #define IGP01E1000_MSE_CHANNEL_D 0x000F
3034 #define IGP01E1000_MSE_CHANNEL_C 0x00F0
3035 #define IGP01E1000_MSE_CHANNEL_B 0x0F00
3036 #define IGP01E1000_MSE_CHANNEL_A 0xF000
3037 
3038 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
3039 #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
3040 #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
3041 
3042 /* IGP01E1000 DSP reset macros */
3043 #define DSP_RESET_ENABLE 0x0
3044 #define DSP_RESET_DISABLE 0x2
3045 #define E1000_MAX_DSP_RESETS 10
3046 
3047 /* IGP01E1000 & IGP02E1000 AGC Registers */
3048 
3049 #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
3050 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
3051 
3052 /* IGP02E1000 AGC Register Length 9-bit mask */
3053 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
3054 
3055 /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
3056 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
3057 #define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113
3058 
3059 /* The precision error of the cable length is +/- 10 meters */
3060 #define IGP01E1000_AGC_RANGE 10
3061 #define IGP02E1000_AGC_RANGE 15
3062 
3063 /* IGP01E1000 PCS Initialization register */
3064 /* bits 3:6 in the PCS registers stores the channels polarity */
3065 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
3066 
3067 /* IGP01E1000 GMII FIFO Register */
3068 #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
3069  * on Link-Up */
3070 #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
3071 
3072 /* IGP01E1000 Analog Register */
3073 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
3074 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
3075 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
3076 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
3077 
3078 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
3079 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
3080 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
3081 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
3082 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
3083 
3084 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
3085 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
3086 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
3087 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
3088 
3089 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
3090 #define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
3091 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */
3092 #define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
3093 #define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */
3094 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
3095 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */
3096 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */
3097 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */
3098 #define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */
3099 #define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
3100 #define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
3101 #define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */
3102 #define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
3103 #define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
3104 #define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
3105 #define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
3106 #define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
3107 
3108 /* PHY Specific Status Register (Page 0, Register 17) */
3109 #define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
3110 #define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
3111 #define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
3112 #define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
3113 #define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
3114 #define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
3115 #define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
3116 #define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
3117 #define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
3118 #define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
3119 #define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
3120 #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
3121 #define GG82563_PSSR_SPEED_MASK 0xC000
3122 #define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
3123 #define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
3124 #define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
3125 
3126 /* PHY Specific Status Register 2 (Page 0, Register 19) */
3127 #define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
3128 #define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
3129 #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
3130 #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
3131 #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
3132 #define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */
3133 #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
3134 #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
3135 #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
3136 #define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
3137 #define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
3138 #define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
3139 #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
3140 
3141 /* PHY Specific Control Register 2 (Page 0, Register 26) */
3142 #define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */
3143 #define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
3144 #define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */
3145 #define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */
3146 #define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */
3147 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */
3148 #define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */
3149 #define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
3150 #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
3151 #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
3152 
3153 /* MAC Specific Control Register (Page 2, Register 21) */
3154 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
3155 #define GG82563_MSCR_TX_CLK_MASK 0x0007
3156 #define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
3157 #define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
3158 #define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
3159 #define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
3160 
3161 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
3162 
3163 /* DSP Distance Register (Page 5, Register 26) */
3164 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
3165  1 = 50-80M;
3166  2 = 80-110M;
3167  3 = 110-140M;
3168  4 = >140M */
3169 
3170 /* Kumeran Mode Control Register (Page 193, Register 16) */
3171 #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */
3172 #define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
3173 #define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
3174 #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
3175 #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */
3176 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
3177 
3178 /* Power Management Control Register (Page 193, Register 20) */
3179 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES Electrical Idle */
3180 #define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
3181 #define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
3182 #define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */
3183 #define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */
3184 #define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */
3185 #define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */
3186 #define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
3187 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
3188 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
3189 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
3190 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
3191 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
3192 
3193 /* In-Band Control Register (Page 194, Register 18) */
3194 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
3195 
3196 
3197 /* Bit definitions for valid PHY IDs. */
3198 /* I = Integrated
3199  * E = External
3200  */
3201 #define M88E1000_E_PHY_ID 0x01410C50
3202 #define M88E1000_I_PHY_ID 0x01410C30
3203 #define M88E1011_I_PHY_ID 0x01410C20
3204 #define IGP01E1000_I_PHY_ID 0x02A80380
3205 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
3206 #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
3207 #define M88E1011_I_REV_4 0x04
3208 #define M88E1111_I_PHY_ID 0x01410CC0
3209 #define L1LXT971A_PHY_ID 0x001378E0
3210 #define GG82563_E_PHY_ID 0x01410CA0
3211 
3212 
3213 /* Bits...
3214  * 15-5: page
3215  * 4-0: register offset
3216  */
3217 #define PHY_PAGE_SHIFT 5
3218 #define PHY_REG(page, reg) \
3219  (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
3220 
3221 #define IGP3_PHY_PORT_CTRL \
3222  PHY_REG(769, 17) /* Port General Configuration */
3223 #define IGP3_PHY_RATE_ADAPT_CTRL \
3224  PHY_REG(769, 25) /* Rate Adapter Control Register */
3225 
3226 #define IGP3_KMRN_FIFO_CTRL_STATS \
3227  PHY_REG(770, 16) /* KMRN FIFO's control/status register */
3228 #define IGP3_KMRN_POWER_MNG_CTRL \
3229  PHY_REG(770, 17) /* KMRN Power Management Control Register */
3230 #define IGP3_KMRN_INBAND_CTRL \
3231  PHY_REG(770, 18) /* KMRN Inband Control Register */
3232 #define IGP3_KMRN_DIAG \
3233  PHY_REG(770, 19) /* KMRN Diagnostic register */
3234 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
3235 #define IGP3_KMRN_ACK_TIMEOUT \
3236  PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
3237 
3238 #define IGP3_VR_CTRL \
3239  PHY_REG(776, 18) /* Voltage regulator control register */
3240 #define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
3241 
3242 #define IGP3_CAPABILITY \
3243  PHY_REG(776, 19) /* IGP3 Capability Register */
3244 
3245 /* Capabilities for SKU Control */
3246 #define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
3247 #define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
3248 #define IGP3_CAP_ASF 0x0004 /* Support ASF */
3249 #define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
3250 #define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
3251 #define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
3252 #define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
3253 #define IGP3_CAP_RSS 0x0080 /* Support RSS */
3254 #define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
3255 #define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
3256 
3257 #define IGP3_PPC_JORDAN_EN 0x0001
3258 #define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
3259 
3260 #define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001
3261 #define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E
3262 #define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
3263 #define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
3264 
3265 #define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
3266 #define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
3267 
3268 #define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
3269 #define IGP3_KMRN_EC_DIS_INBAND 0x0080
3270 
3271 #define IGP03E1000_E_PHY_ID 0x02A80390
3272 #define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
3273 #define IFE_PLUS_E_PHY_ID 0x02A80320
3274 #define IFE_C_E_PHY_ID 0x02A80310
3275 
3276 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
3277 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
3278 #define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
3279 #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */
3280 #define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
3281 #define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
3282 #define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
3283 #define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
3284 #define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
3285 #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
3286 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
3287 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
3288 #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
3289 
3290 #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */
3291 #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
3292 #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
3293 #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
3294 #define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
3295 #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
3296 #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
3297 #define IFE_PESC_POLARITY_REVERSED_SHIFT 8
3298 
3299 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */
3300 #define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
3301 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
3302 #define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
3303 #define IFE_PSC_FORCE_POLARITY_SHIFT 5
3304 #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
3305 
3306 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
3307 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
3308 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
3309 #define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorthm is completed */
3310 #define IFE_PMC_MDIX_MODE_SHIFT 6
3311 #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
3312 
3313 #define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
3314 #define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
3315 #define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
3316 #define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
3317 #define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
3318 #define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
3319 #define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
3320 #define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
3321 #define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
3322 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
3323 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
3324 
3325 #define ICH8_FLASH_COMMAND_TIMEOUT 500 /* 500 ms , should be adjusted */
3326 #define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles , should be adjusted */
3327 #define ICH8_FLASH_SEG_SIZE_256 256
3328 #define ICH8_FLASH_SEG_SIZE_4K 4096
3329 #define ICH8_FLASH_SEG_SIZE_64K 65536
3330 
3331 #define ICH8_CYCLE_READ 0x0
3332 #define ICH8_CYCLE_RESERVED 0x1
3333 #define ICH8_CYCLE_WRITE 0x2
3334 #define ICH8_CYCLE_ERASE 0x3
3335 
3336 #define ICH8_FLASH_GFPREG 0x0000
3337 #define ICH8_FLASH_HSFSTS 0x0004
3338 #define ICH8_FLASH_HSFCTL 0x0006
3339 #define ICH8_FLASH_FADDR 0x0008
3340 #define ICH8_FLASH_FDATA0 0x0010
3341 #define ICH8_FLASH_FRACC 0x0050
3342 #define ICH8_FLASH_FREG0 0x0054
3343 #define ICH8_FLASH_FREG1 0x0058
3344 #define ICH8_FLASH_FREG2 0x005C
3345 #define ICH8_FLASH_FREG3 0x0060
3346 #define ICH8_FLASH_FPR0 0x0074
3347 #define ICH8_FLASH_FPR1 0x0078
3348 #define ICH8_FLASH_SSFSTS 0x0090
3349 #define ICH8_FLASH_SSFCTL 0x0092
3350 #define ICH8_FLASH_PREOP 0x0094
3351 #define ICH8_FLASH_OPTYPE 0x0096
3352 #define ICH8_FLASH_OPMENU 0x0098
3353 
3354 #define ICH8_FLASH_REG_MAPSIZE 0x00A0
3355 #define ICH8_FLASH_SECTOR_SIZE 4096
3356 #define ICH8_GFPREG_BASE_MASK 0x1FFF
3357 #define ICH8_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3358 
3359 /* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
3360 /* Offset 04h HSFSTS */
3361 union ich8_hws_flash_status {
3362  struct ich8_hsfsts {
3363 #ifdef E1000_BIG_ENDIAN
3364  uint16_t reserved2 :6;
3365  uint16_t fldesvalid :1;
3366  uint16_t flockdn :1;
3367  uint16_t flcdone :1;
3368  uint16_t flcerr :1;
3369  uint16_t dael :1;
3370  uint16_t berasesz :2;
3371  uint16_t flcinprog :1;
3372  uint16_t reserved1 :2;
3373 #else
3374  uint16_t flcdone :1; /* bit 0 Flash Cycle Done */
3375  uint16_t flcerr :1; /* bit 1 Flash Cycle Error */
3376  uint16_t dael :1; /* bit 2 Direct Access error Log */
3377  uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */
3378  uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */
3379  uint16_t reserved1 :2; /* bit 13:6 Reserved */
3380  uint16_t reserved2 :6; /* bit 13:6 Reserved */
3381  uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */
3382  uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */
3383 #endif
3384  } hsf_status;
3385  uint16_t regval;
3386 };
3387 
3388 /* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
3389 /* Offset 06h FLCTL */
3390 union ich8_hws_flash_ctrl {
3391  struct ich8_hsflctl {
3392 #ifdef E1000_BIG_ENDIAN
3393  uint16_t fldbcount :2;
3394  uint16_t flockdn :6;
3395  uint16_t flcgo :1;
3396  uint16_t flcycle :2;
3397  uint16_t reserved :5;
3398 #else
3399  uint16_t flcgo :1; /* 0 Flash Cycle Go */
3400  uint16_t flcycle :2; /* 2:1 Flash Cycle */
3401  uint16_t reserved :5; /* 7:3 Reserved */
3402  uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */
3403  uint16_t flockdn :6; /* 15:10 Reserved */
3404 #endif
3405  } hsf_ctrl;
3406  uint16_t regval;
3407 };
3408 
3409 /* ICH8 Flash Region Access Permissions */
3410 union ich8_hws_flash_regacc {
3411  struct ich8_flracc {
3412 #ifdef E1000_BIG_ENDIAN
3413  uint32_t gmwag :8;
3414  uint32_t gmrag :8;
3415  uint32_t grwa :8;
3416  uint32_t grra :8;
3417 #else
3418  uint32_t grra :8; /* 0:7 GbE region Read Access */
3419  uint32_t grwa :8; /* 8:15 GbE region Write Access */
3420  uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */
3421  uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */
3422 #endif
3423  } hsf_flregacc;
3424  uint16_t regval;
3425 };
3426 
3427 /* Miscellaneous PHY bit definitions. */
3428 #define PHY_PREAMBLE 0xFFFFFFFF
3429 #define PHY_SOF 0x01
3430 #define PHY_OP_READ 0x02
3431 #define PHY_OP_WRITE 0x01
3432 #define PHY_TURNAROUND 0x02
3433 #define PHY_PREAMBLE_SIZE 32
3434 #define MII_CR_SPEED_1000 0x0040
3435 #define MII_CR_SPEED_100 0x2000
3436 #define MII_CR_SPEED_10 0x0000
3437 #define E1000_PHY_ADDRESS 0x01
3438 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
3439 #define PHY_FORCE_TIME 20 /* 2.0 Seconds */
3440 #define PHY_REVISION_MASK 0xFFFFFFF0
3441 #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
3442 #define REG4_SPEED_MASK 0x01E0
3443 #define REG9_SPEED_MASK 0x0300
3444 #define ADVERTISE_10_HALF 0x0001
3445 #define ADVERTISE_10_FULL 0x0002
3446 #define ADVERTISE_100_HALF 0x0004
3447 #define ADVERTISE_100_FULL 0x0008
3448 #define ADVERTISE_1000_HALF 0x0010
3449 #define ADVERTISE_1000_FULL 0x0020
3450 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
3451 #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
3452 #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
3453 
3454 #endif /* _E1000_HW_H_ */