Xenomai  3.0.8
e1000_osdep.h
1 /*******************************************************************************
2 
3 
4  Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms of the GNU General Public License as published by the Free
8  Software Foundation; either version 2 of the License, or (at your option)
9  any later version.
10 
11  This program is distributed in the hope that it will be useful, but WITHOUT
12  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14  more details.
15 
16  You should have received a copy of the GNU General Public License along with
17  this program; if not, write to the Free Software Foundation, Inc., 59
18  Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 
20  The full GNU General Public License is included in this distribution in the
21  file called LICENSE.
22 
23  Contact Information:
24  Linux NICS <linux.nics@intel.com>
25  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
26  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 
28 *******************************************************************************/
29 
30 
31 /* glue for the OS independent part of e1000
32  * includes register access macros
33  */
34 
35 #ifndef _E1000_OSDEP_H_
36 #define _E1000_OSDEP_H_
37 
38 #include <linux/types.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <asm/io.h>
42 #include <linux/interrupt.h>
43 #include <linux/sched.h>
44 #include "kcompat.h"
45 
46 #define usec_delay(x) udelay(x)
47 #ifndef msec_delay
48 #define msec_delay(x) do { if(in_interrupt()) { \
49  /* Don't mdelay in interrupt context! */ \
50  BUG(); \
51  } else { \
52  msleep(x); \
53  } } while (0)
54 
55 /* Some workarounds require millisecond delays and are run during interrupt
56  * context. Most notably, when establishing link, the phy may need tweaking
57  * but cannot process phy register reads/writes faster than millisecond
58  * intervals...and we establish link due to a "link status change" interrupt.
59  */
60 #define msec_delay_irq(x) mdelay(x)
61 #endif
62 
63 #define PCI_COMMAND_REGISTER PCI_COMMAND
64 #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
65 
66 typedef enum {
67 #undef FALSE
68  FALSE = 0,
69 #undef TRUE
70  TRUE = 1
71 } boolean_t;
72 
73 #define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B)
74 
75 #ifdef DBG
76 #define DEBUGOUT(S) printk(KERN_DEBUG S "\n")
77 #define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A)
78 #else
79 #define DEBUGOUT(S)
80 #define DEBUGOUT1(S, A...)
81 #endif
82 
83 #define DEBUGFUNC(F) DEBUGOUT(F)
84 #define DEBUGOUT2 DEBUGOUT1
85 #define DEBUGOUT3 DEBUGOUT2
86 #define DEBUGOUT7 DEBUGOUT3
87 
88 #ifdef __BIG_ENDIAN
89 #define E1000_BIG_ENDIAN __BIG_ENDIAN
90 #endif
91 
92 #define E1000_WRITE_REG(a, reg, value) ( \
93  writel((value), ((a)->hw_addr + \
94  (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg))))
95 
96 #define E1000_READ_REG(a, reg) ( \
97  readl((a)->hw_addr + \
98  (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg)))
99 
100 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
101  writel((value), ((a)->hw_addr + \
102  (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
103  ((offset) << 2))))
104 
105 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
106  readl((a)->hw_addr + \
107  (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
108  ((offset) << 2)))
109 
110 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
111 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
112 
113 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
114  writew((value), ((a)->hw_addr + \
115  (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
116  ((offset) << 1))))
117 
118 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
119  readw((a)->hw_addr + \
120  (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
121  ((offset) << 1)))
122 
123 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
124  writeb((value), ((a)->hw_addr + \
125  (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
126  (offset))))
127 
128 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
129  readb((a)->hw_addr + \
130  (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
131  (offset)))
132 
133 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
134 
135 #define E1000_WRITE_ICH8_REG(a, reg, value) ( \
136  writel((value), ((a)->flash_address + reg)))
137 
138 #define E1000_READ_ICH8_REG(a, reg) ( \
139  readl((a)->flash_address + reg))
140 
141 #define E1000_WRITE_ICH8_REG16(a, reg, value) ( \
142  writew((value), ((a)->flash_address + reg)))
143 
144 #define E1000_READ_ICH8_REG16(a, reg) ( \
145  readw((a)->flash_address + reg))
146 
147 
148 #endif /* _E1000_OSDEP_H_ */