Xenomai  3.0.8
e1000_80003es2lan.h
1 /*******************************************************************************
2 
3  Intel PRO/1000 Linux driver
4  Copyright(c) 1999 - 2008 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Contact Information:
23  Linux NICS <linux.nics@intel.com>
24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #ifndef _E1000_80003ES2LAN_H_
30 #define _E1000_80003ES2LAN_H_
31 
32 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
33 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
34 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
35 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
36 
37 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
38 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
39 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
40 
41 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
42 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
43 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
44 
45 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
46 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
47 
48 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
49 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
50 
51 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
52 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disabled */
53 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
54 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
55 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
56 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
57 
58 /* PHY Specific Control Register 2 (Page 0, Register 26) */
59 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
60  /* 1=Reverse Auto-Negotiation */
61 
62 /* MAC Specific Control Register (Page 2, Register 21) */
63 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
64 #define GG82563_MSCR_TX_CLK_MASK 0x0007
65 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
66 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
67 #define GG82563_MSCR_TX_CLK_1000MBPS_2_5 0x0006
68 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
69 
70 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
71 
72 /* DSP Distance Register (Page 5, Register 26) */
73 /*
74  * 0 = <50M
75  * 1 = 50-80M
76  * 2 = 80-100M
77  * 3 = 110-140M
78  * 4 = >140M
79  */
80 #define GG82563_DSPD_CABLE_LENGTH 0x0007
81 
82 /* Kumeran Mode Control Register (Page 193, Register 16) */
83 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
84 
85 /* Max number of times Kumeran read/write should be validated */
86 #define GG82563_MAX_KMRN_RETRY 0x5
87 
88 /* Power Management Control Register (Page 193, Register 20) */
89 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
90  /* 1=Enable SERDES Electrical Idle */
91 
92 /* In-Band Control Register (Page 194, Register 18) */
93 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
94 
95 #endif