Xenomai  3.0.8
e1000_82575.h
1 /* Intel(R) Gigabit Ethernet Linux driver
2  * Copyright(c) 2007-2014 Intel Corporation.
3  * RTnet port 2009 Vladimir Zapolskiy <vladimir.zapolskiy@siemens.com>
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, see <http://www.gnu.org/licenses/>.
16  *
17  * The full GNU General Public License is included in this distribution in
18  * the file called "COPYING".
19  *
20  * Contact Information:
21  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23  */
24 
25 #ifndef _E1000_82575_H_
26 #define _E1000_82575_H_
27 
28 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw);
29 void igb_power_up_serdes_link_82575(struct e1000_hw *hw);
30 void igb_power_down_phy_copper_82575(struct e1000_hw *hw);
31 void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
32 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
33  u8 *data);
34 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
35  u8 data);
36 
37 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
38  (ID_LED_DEF1_DEF2 << 8) | \
39  (ID_LED_DEF1_DEF2 << 4) | \
40  (ID_LED_OFF1_ON2))
41 
42 #define E1000_RAR_ENTRIES_82575 16
43 #define E1000_RAR_ENTRIES_82576 24
44 #define E1000_RAR_ENTRIES_82580 24
45 #define E1000_RAR_ENTRIES_I350 32
46 
47 #define E1000_SW_SYNCH_MB 0x00000100
48 #define E1000_STAT_DEV_RST_SET 0x00100000
49 #define E1000_CTRL_DEV_RST 0x20000000
50 
51 /* SRRCTL bit definitions */
52 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
53 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
54 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
55 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
56 #define E1000_SRRCTL_DROP_EN 0x80000000
57 #define E1000_SRRCTL_TIMESTAMP 0x40000000
58 
59 
60 #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
61 #define E1000_MRQC_ENABLE_VMDQ 0x00000003
62 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
63 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
64 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
65 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
66 
67 #define E1000_EICR_TX_QUEUE ( \
68  E1000_EICR_TX_QUEUE0 | \
69  E1000_EICR_TX_QUEUE1 | \
70  E1000_EICR_TX_QUEUE2 | \
71  E1000_EICR_TX_QUEUE3)
72 
73 #define E1000_EICR_RX_QUEUE ( \
74  E1000_EICR_RX_QUEUE0 | \
75  E1000_EICR_RX_QUEUE1 | \
76  E1000_EICR_RX_QUEUE2 | \
77  E1000_EICR_RX_QUEUE3)
78 
79 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
80 #define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
81 #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
82 
83 /* Receive Descriptor - Advanced */
84 union e1000_adv_rx_desc {
85  struct {
86  __le64 pkt_addr; /* Packet buffer address */
87  __le64 hdr_addr; /* Header buffer address */
88  } read;
89  struct {
90  struct {
91  struct {
92  __le16 pkt_info; /* RSS type, Packet type */
93  __le16 hdr_info; /* Split Head, buf len */
94  } lo_dword;
95  union {
96  __le32 rss; /* RSS Hash */
97  struct {
98  __le16 ip_id; /* IP id */
99  __le16 csum; /* Packet Checksum */
100  } csum_ip;
101  } hi_dword;
102  } lower;
103  struct {
104  __le32 status_error; /* ext status/error */
105  __le16 length; /* Packet length */
106  __le16 vlan; /* VLAN tag */
107  } upper;
108  } wb; /* writeback */
109 };
110 
111 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
112 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5
113 #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
114 #define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
115 
116 /* Transmit Descriptor - Advanced */
117 union e1000_adv_tx_desc {
118  struct {
119  __le64 buffer_addr; /* Address of descriptor's data buf */
120  __le32 cmd_type_len;
121  __le32 olinfo_status;
122  } read;
123  struct {
124  __le64 rsvd; /* Reserved */
125  __le32 nxtseq_seed;
126  __le32 status;
127  } wb;
128 };
129 
130 /* Adv Transmit Descriptor Config Masks */
131 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
132 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
133 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
134 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
135 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
136 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
137 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
138 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
139 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
140 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
141 
142 /* Context descriptors */
143 struct e1000_adv_tx_context_desc {
144  __le32 vlan_macip_lens;
145  __le32 seqnum_seed;
146  __le32 type_tucmd_mlhl;
147  __le32 mss_l4len_idx;
148 };
149 
150 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
151 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
152 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
153 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
154 /* IPSec Encrypt Enable for ESP */
155 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
156 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
157 /* Adv ctxt IPSec SA IDX mask */
158 /* Adv ctxt IPSec ESP len mask */
159 
160 /* Additional Transmit Descriptor Control definitions */
161 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
162 /* Tx Queue Arbitration Priority 0=low, 1=high */
163 
164 /* Additional Receive Descriptor Control definitions */
165 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
166 
167 /* Direct Cache Access (DCA) definitions */
168 #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
169 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
170 
171 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
172 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
173 #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
174 #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
175 #define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
176 
177 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
178 #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
179 #define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
180 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
181 #define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
182 
183 /* Additional DCA related definitions, note change in position of CPUID */
184 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
185 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
186 #define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
187 #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
188 
189 /* ETQF register bit definitions */
190 #define E1000_ETQF_FILTER_ENABLE (1 << 26)
191 #define E1000_ETQF_1588 (1 << 30)
192 
193 /* FTQF register bit definitions */
194 #define E1000_FTQF_VF_BP 0x00008000
195 #define E1000_FTQF_1588_TIME_STAMP 0x08000000
196 #define E1000_FTQF_MASK 0xF0000000
197 #define E1000_FTQF_MASK_PROTO_BP 0x10000000
198 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
199 
200 #define E1000_NVM_APME_82575 0x0400
201 #define MAX_NUM_VFS 8
202 
203 #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
204 #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
205 #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
206 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
207 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */
208 
209 /* Easy defines for setting default pool, would normally be left a zero */
210 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
211 #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
212 
213 /* Other useful VMD_CTL register defines */
214 #define E1000_VT_CTL_IGNORE_MAC (1 << 28)
215 #define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29)
216 #define E1000_VT_CTL_VM_REPL_EN (1 << 30)
217 
218 /* Per VM Offload register setup */
219 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
220 #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
221 #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
222 #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
223 #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
224 #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
225 #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
226 #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
227 #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
228 #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
229 
230 #define E1000_DVMOLR_HIDEVLAN 0x20000000 /* Hide vlan enable */
231 #define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
232 #define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */
233 
234 #define E1000_VLVF_ARRAY_SIZE 32
235 #define E1000_VLVF_VLANID_MASK 0x00000FFF
236 #define E1000_VLVF_POOLSEL_SHIFT 12
237 #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
238 #define E1000_VLVF_LVLAN 0x00100000
239 #define E1000_VLVF_VLANID_ENABLE 0x80000000
240 
241 #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
242 #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
243 
244 #define E1000_IOVCTL 0x05BBC
245 #define E1000_IOVCTL_REUSE_VFQ 0x00000001
246 
247 #define E1000_RPLOLR_STRVLAN 0x40000000
248 #define E1000_RPLOLR_STRCRC 0x80000000
249 
250 #define E1000_DTXCTL_8023LL 0x0004
251 #define E1000_DTXCTL_VLAN_ADDED 0x0008
252 #define E1000_DTXCTL_OOS_ENABLE 0x0010
253 #define E1000_DTXCTL_MDP_EN 0x0020
254 #define E1000_DTXCTL_SPOOF_INT 0x0040
255 
256 #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14)
257 
258 #define ALL_QUEUES 0xFFFF
259 
260 /* RX packet buffer size defines */
261 #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
262 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
263 void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
264 void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
265 u16 igb_rxpbs_adjust_82580(u32 data);
266 s32 igb_read_emi_reg(struct e1000_hw *, u16 addr, u16 *data);
267 s32 igb_set_eee_i350(struct e1000_hw *, bool adv1G, bool adv100M);
268 s32 igb_set_eee_i354(struct e1000_hw *, bool adv1G, bool adv100M);
269 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status);
270 
271 #define E1000_I2C_THERMAL_SENSOR_ADDR 0xF8
272 #define E1000_EMC_INTERNAL_DATA 0x00
273 #define E1000_EMC_INTERNAL_THERM_LIMIT 0x20
274 #define E1000_EMC_DIODE1_DATA 0x01
275 #define E1000_EMC_DIODE1_THERM_LIMIT 0x19
276 #define E1000_EMC_DIODE2_DATA 0x23
277 #define E1000_EMC_DIODE2_THERM_LIMIT 0x1A
278 #define E1000_EMC_DIODE3_DATA 0x2A
279 #define E1000_EMC_DIODE3_THERM_LIMIT 0x30
280 #endif