Xenomai  3.0.8
e1000_ich8lan.h
1 /*******************************************************************************
2 
3  Intel PRO/1000 Linux driver
4  Copyright(c) 1999 - 2008 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Contact Information:
23  Linux NICS <linux.nics@intel.com>
24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #ifndef _E1000_ICH8LAN_H_
30 #define _E1000_ICH8LAN_H_
31 
32 #define ICH_FLASH_GFPREG 0x0000
33 #define ICH_FLASH_HSFSTS 0x0004
34 #define ICH_FLASH_HSFCTL 0x0006
35 #define ICH_FLASH_FADDR 0x0008
36 #define ICH_FLASH_FDATA0 0x0010
37 
38 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
39 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
40 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
41 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
42 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
43 
44 #define ICH_CYCLE_READ 0
45 #define ICH_CYCLE_WRITE 2
46 #define ICH_CYCLE_ERASE 3
47 
48 #define FLASH_GFPREG_BASE_MASK 0x1FFF
49 #define FLASH_SECTOR_ADDR_SHIFT 12
50 
51 #define E1000_SHADOW_RAM_WORDS 2048
52 
53 #define ICH_FLASH_SEG_SIZE_256 256
54 #define ICH_FLASH_SEG_SIZE_4K 4096
55 #define ICH_FLASH_SEG_SIZE_8K 8192
56 #define ICH_FLASH_SEG_SIZE_64K 65536
57 #define ICH_FLASH_SECTOR_SIZE 4096
58 
59 #define ICH_FLASH_REG_MAPSIZE 0x00A0
60 
61 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
62 #define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */
63 /* FW established a valid mode */
64 #define E1000_ICH_FWSM_FW_VALID 0x00008000
65 
66 #define E1000_ICH_MNG_IAMT_MODE 0x2
67 
68 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
69  (ID_LED_DEF1_OFF2 << 8) | \
70  (ID_LED_DEF1_ON2 << 4) | \
71  (ID_LED_DEF1_DEF2))
72 
73 #define E1000_ICH_NVM_SIG_WORD 0x13
74 #define E1000_ICH_NVM_SIG_MASK 0xC000
75 
76 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
77 
78 #define E1000_FEXTNVM_SW_CONFIG 1
79 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
80 
81 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
82 
83 #define E1000_ICH_RAR_ENTRIES 7
84 
85 #define PHY_PAGE_SHIFT 5
86 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
87  ((reg) & MAX_PHY_REG_ADDRESS))
88 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
89 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
90 #define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
91 #define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */
92 
93 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
94 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
95 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
96 #define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020
97 
98 /*
99  * Additional interrupts need to be handled for ICH family:
100  * DSW = The FW changed the status of the DISSW bit in FWSM
101  * PHYINT = The LAN connected device generates an interrupt
102  * EPRST = Manageability reset event
103  */
104 #define IMS_ICH_ENABLE_MASK (\
105  E1000_IMS_DSW | \
106  E1000_IMS_PHYINT | \
107  E1000_IMS_EPRST)
108 
109 
110 #endif