Xenomai  3.0.8
e1000_defines.h
1 /*******************************************************************************
2 
3  Intel PRO/1000 Linux driver
4  Copyright(c) 1999 - 2008 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Contact Information:
23  Linux NICS <linux.nics@intel.com>
24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #ifndef _E1000_DEFINES_H_
30 #define _E1000_DEFINES_H_
31 
32 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
33 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
34 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
35 
36 /* Definitions for power management and wakeup registers */
37 /* Wake Up Control */
38 #define E1000_WUC_APME 0x00000001 /* APM Enable */
39 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
40 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
41 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
42 #define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */
43 #define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */
44 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */
45 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
46 
47 /* Wake Up Filter Control */
48 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
49 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
50 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
51 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
52 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
53 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
54 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
55 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
56 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
57 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
58 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
59 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
60 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
61 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
62 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
63 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
64 
65 /* Wake Up Status */
66 #define E1000_WUS_LNKC E1000_WUFC_LNKC
67 #define E1000_WUS_MAG E1000_WUFC_MAG
68 #define E1000_WUS_EX E1000_WUFC_EX
69 #define E1000_WUS_MC E1000_WUFC_MC
70 #define E1000_WUS_BC E1000_WUFC_BC
71 #define E1000_WUS_ARP E1000_WUFC_ARP
72 #define E1000_WUS_IPV4 E1000_WUFC_IPV4
73 #define E1000_WUS_IPV6 E1000_WUFC_IPV6
74 #define E1000_WUS_FLX0 E1000_WUFC_FLX0
75 #define E1000_WUS_FLX1 E1000_WUFC_FLX1
76 #define E1000_WUS_FLX2 E1000_WUFC_FLX2
77 #define E1000_WUS_FLX3 E1000_WUFC_FLX3
78 #define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS
79 
80 /* Wake Up Packet Length */
81 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
82 
83 /* Four Flexible Filters are supported */
84 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
85 
86 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
87 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
88 
89 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
90 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
91 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
92 
93 /* Extended Device Control */
94 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
95 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
96 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
97 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
98 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
99 /* Reserved (bits 4,5) in >= 82575 */
100 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
101 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
102 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
103 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
104 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
105 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
106 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
107 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
108 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
109 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
110 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
111 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
112 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
113 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
114 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
115 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
116 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
117 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
118 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
119 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
120 #define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000
121 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
122 #define E1000_CTRL_EXT_EIAME 0x01000000
123 #define E1000_CTRL_EXT_IRCA 0x00000001
124 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
125 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
126 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
127 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
128 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
129 #define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */
130 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
131 /* IAME enable bit (27) was removed in >= 82575 */
132 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
133 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
134 #define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
135 #define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
136 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
137 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
138 #define E1000_I2CCMD_REG_ADDR_SHIFT 16
139 #define E1000_I2CCMD_REG_ADDR 0x00FF0000
140 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24
141 #define E1000_I2CCMD_PHY_ADDR 0x07000000
142 #define E1000_I2CCMD_OPCODE_READ 0x08000000
143 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
144 #define E1000_I2CCMD_RESET 0x10000000
145 #define E1000_I2CCMD_READY 0x20000000
146 #define E1000_I2CCMD_INTERRUPT_ENA 0x40000000
147 #define E1000_I2CCMD_ERROR 0x80000000
148 #define E1000_MAX_SGMII_PHY_REG_ADDR 255
149 #define E1000_I2CCMD_PHY_TIMEOUT 200
150 
151 /* Receive Decriptor bit definitions */
152 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
153 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
154 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
155 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
156 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
157 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
158 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
159 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
160 #define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
161 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
162 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
163 #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
164 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
165 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
166 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
167 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
168 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
169 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
170 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
171 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
172 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
173 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
174 #define E1000_RXD_SPC_PRI_SHIFT 13
175 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
176 #define E1000_RXD_SPC_CFI_SHIFT 12
177 
178 #define E1000_RXDEXT_STATERR_CE 0x01000000
179 #define E1000_RXDEXT_STATERR_SE 0x02000000
180 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
181 #define E1000_RXDEXT_STATERR_CXE 0x10000000
182 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
183 #define E1000_RXDEXT_STATERR_IPE 0x40000000
184 #define E1000_RXDEXT_STATERR_RXE 0x80000000
185 
186 /* mask to determine if packets should be dropped due to frame errors */
187 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
188  E1000_RXD_ERR_CE | \
189  E1000_RXD_ERR_SE | \
190  E1000_RXD_ERR_SEQ | \
191  E1000_RXD_ERR_CXE | \
192  E1000_RXD_ERR_RXE)
193 
194 /* Same mask, but for extended and packet split descriptors */
195 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
196  E1000_RXDEXT_STATERR_CE | \
197  E1000_RXDEXT_STATERR_SE | \
198  E1000_RXDEXT_STATERR_SEQ | \
199  E1000_RXDEXT_STATERR_CXE | \
200  E1000_RXDEXT_STATERR_RXE)
201 
202 #define E1000_MRQC_ENABLE_MASK 0x00000007
203 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
204 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004
205 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
206 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
207 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
208 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
209 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
210 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
211 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
212 
213 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
214 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
215 
216 /* Management Control */
217 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
218 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
219 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
220 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
221 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
222 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
223 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
224 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
225 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
226 /* Enable Neighbor Discovery Filtering */
227 #define E1000_MANC_NEIGHBOR_EN 0x00004000
228 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
229 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
230 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
231 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
232 #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
233 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
234 /* Enable MAC address filtering */
235 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
236 /* Enable MNG packets to host memory */
237 #define E1000_MANC_EN_MNG2HOST 0x00200000
238 /* Enable IP address filtering */
239 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000
240 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
241 #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
242 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
243 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
244 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
245 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
246 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
247 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
248 
249 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
250 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
251 
252 /* Receive Control */
253 #define E1000_RCTL_RST 0x00000001 /* Software reset */
254 #define E1000_RCTL_EN 0x00000002 /* enable */
255 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
256 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
257 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
258 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
259 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
260 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
261 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
262 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
263 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
264 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
265 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
266 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
267 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
268 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
269 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
270 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
271 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
272 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
273 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
274 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
275 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
276 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
277 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
278 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
279 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
280 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
281 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
282 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
283 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
284 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
285 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
286 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
287 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
288 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
289 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
290 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
291 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
292 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
293 
294 /*
295  * Use byte values for the following shift parameters
296  * Usage:
297  * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
298  * E1000_PSRCTL_BSIZE0_MASK) |
299  * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
300  * E1000_PSRCTL_BSIZE1_MASK) |
301  * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
302  * E1000_PSRCTL_BSIZE2_MASK) |
303  * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
304  * E1000_PSRCTL_BSIZE3_MASK))
305  * where value0 = [128..16256], default=256
306  * value1 = [1024..64512], default=4096
307  * value2 = [0..64512], default=4096
308  * value3 = [0..64512], default=0
309  */
310 
311 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
312 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
313 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
314 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
315 
316 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
317 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
318 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
319 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
320 
321 /* SWFW_SYNC Definitions */
322 #define E1000_SWFW_EEP_SM 0x1
323 #define E1000_SWFW_PHY0_SM 0x2
324 #define E1000_SWFW_PHY1_SM 0x4
325 #define E1000_SWFW_CSR_SM 0x8
326 
327 /* FACTPS Definitions */
328 #define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */
329 /* Device Control */
330 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
331 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
332 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
333 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
334 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
335 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
336 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
337 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
338 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
339 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
340 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
341 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
342 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
343 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
344 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
345 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
346 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
347 #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
348 #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
349 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
350 #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
351 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
352 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
353 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
354 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
355 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
356 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
357 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
358 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
359 #define E1000_CTRL_RST 0x04000000 /* Global reset */
360 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
361 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
362 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
363 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
364 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
365 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
366 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
367 
368 /* Bit definitions for the Management Data IO (MDIO) and Management Data
369  * Clock (MDC) pins in the Device Control Register.
370  */
371 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
372 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
373 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
374 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
375 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
376 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
377 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
378 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
379 
380 #define E1000_CONNSW_ENRGSRC 0x4
381 #define E1000_PCS_LCTL_FLV_LINK_UP 1
382 #define E1000_PCS_LCTL_FSV_10 0
383 #define E1000_PCS_LCTL_FSV_100 2
384 #define E1000_PCS_LCTL_FSV_1000 4
385 #define E1000_PCS_LCTL_FDV_FULL 8
386 #define E1000_PCS_LCTL_FSD 0x10
387 #define E1000_PCS_LCTL_FORCE_LINK 0x20
388 #define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40
389 #define E1000_PCS_LCTL_AN_ENABLE 0x10000
390 #define E1000_PCS_LCTL_AN_RESTART 0x20000
391 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
392 #define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000
393 #define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000
394 #define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000
395 #define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000
396 #define E1000_PCS_LCTL_CRS_ON_NI 0x4000000
397 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
398 
399 #define E1000_PCS_LSTS_LINK_OK 1
400 #define E1000_PCS_LSTS_SPEED_10 0
401 #define E1000_PCS_LSTS_SPEED_100 2
402 #define E1000_PCS_LSTS_SPEED_1000 4
403 #define E1000_PCS_LSTS_DUPLEX_FULL 8
404 #define E1000_PCS_LSTS_SYNK_OK 0x10
405 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000
406 #define E1000_PCS_LSTS_AN_PAGE_RX 0x20000
407 #define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000
408 #define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000
409 #define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000
410 
411 /* Device Status */
412 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
413 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
414 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
415 #define E1000_STATUS_FUNC_SHIFT 2
416 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
417 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
418 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
419 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
420 #define E1000_STATUS_SPEED_MASK 0x000000C0
421 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
422 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
423 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
424 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */
425 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
426 #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
427 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
428 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
429 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
430 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
431 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
432 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
433 #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
434 #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
435 #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
436 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
437 #define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
438 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
439 #define E1000_STATUS_FUSE_8 0x04000000
440 #define E1000_STATUS_FUSE_9 0x08000000
441 #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
442 #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
443 
444 /* Constants used to intrepret the masked PCI-X bus speed. */
445 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
446 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
447 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
448 
449 #define SPEED_10 10
450 #define SPEED_100 100
451 #define SPEED_1000 1000
452 #define HALF_DUPLEX 1
453 #define FULL_DUPLEX 2
454 
455 #define PHY_FORCE_TIME 20
456 
457 #define ADVERTISE_10_HALF 0x0001
458 #define ADVERTISE_10_FULL 0x0002
459 #define ADVERTISE_100_HALF 0x0004
460 #define ADVERTISE_100_FULL 0x0008
461 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
462 #define ADVERTISE_1000_FULL 0x0020
463 
464 /* 1000/H is not supported, nor spec-compliant. */
465 #define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
466  ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
467  ADVERTISE_1000_FULL)
468 #define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
469  ADVERTISE_100_HALF | ADVERTISE_100_FULL)
470 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
471 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
472 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
473  ADVERTISE_1000_FULL)
474 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
475 
476 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
477 
478 /* LED Control */
479 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
480 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
481 #define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020
482 #define E1000_LEDCTL_LED0_IVRT 0x00000040
483 #define E1000_LEDCTL_LED0_BLINK 0x00000080
484 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
485 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
486 #define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000
487 #define E1000_LEDCTL_LED1_IVRT 0x00004000
488 #define E1000_LEDCTL_LED1_BLINK 0x00008000
489 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
490 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
491 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
492 #define E1000_LEDCTL_LED2_IVRT 0x00400000
493 #define E1000_LEDCTL_LED2_BLINK 0x00800000
494 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
495 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
496 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
497 #define E1000_LEDCTL_LED3_IVRT 0x40000000
498 #define E1000_LEDCTL_LED3_BLINK 0x80000000
499 
500 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0
501 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
502 #define E1000_LEDCTL_MODE_LINK_UP 0x2
503 #define E1000_LEDCTL_MODE_ACTIVITY 0x3
504 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
505 #define E1000_LEDCTL_MODE_LINK_10 0x5
506 #define E1000_LEDCTL_MODE_LINK_100 0x6
507 #define E1000_LEDCTL_MODE_LINK_1000 0x7
508 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8
509 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
510 #define E1000_LEDCTL_MODE_COLLISION 0xA
511 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB
512 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC
513 #define E1000_LEDCTL_MODE_PAUSED 0xD
514 #define E1000_LEDCTL_MODE_LED_ON 0xE
515 #define E1000_LEDCTL_MODE_LED_OFF 0xF
516 
517 /* Transmit Descriptor bit definitions */
518 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
519 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
520 #define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */
521 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
522 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
523 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
524 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
525 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
526 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
527 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
528 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
529 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
530 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
531 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
532 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
533 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
534 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
535 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
536 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
537 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
538 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
539 /* Extended desc bits for Linksec and timesync */
540 
541 /* Transmit Control */
542 #define E1000_TCTL_RST 0x00000001 /* software reset */
543 #define E1000_TCTL_EN 0x00000002 /* enable tx */
544 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */
545 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
546 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
547 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
548 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
549 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
550 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
551 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
552 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
553 
554 /* Transmit Arbitration Count */
555 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
556 
557 /* SerDes Control */
558 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
559 
560 /* Receive Checksum Control */
561 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
562 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
563 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
564 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
565 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
566 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
567 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
568 
569 /* Header split receive */
570 #define E1000_RFCTL_ISCSI_DIS 0x00000001
571 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
572 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1
573 #define E1000_RFCTL_NFSW_DIS 0x00000040
574 #define E1000_RFCTL_NFSR_DIS 0x00000080
575 #define E1000_RFCTL_NFS_VER_MASK 0x00000300
576 #define E1000_RFCTL_NFS_VER_SHIFT 8
577 #define E1000_RFCTL_IPV6_DIS 0x00000400
578 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
579 #define E1000_RFCTL_ACK_DIS 0x00001000
580 #define E1000_RFCTL_ACKD_DIS 0x00002000
581 #define E1000_RFCTL_IPFRSP_DIS 0x00004000
582 #define E1000_RFCTL_EXTEN 0x00008000
583 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
584 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
585 
586 /* Collision related configuration parameters */
587 #define E1000_COLLISION_THRESHOLD 15
588 #define E1000_CT_SHIFT 4
589 #define E1000_COLLISION_DISTANCE 63
590 #define E1000_COLD_SHIFT 12
591 
592 /* Default values for the transmit IPG register */
593 #define DEFAULT_82542_TIPG_IPGT 10
594 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
595 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
596 
597 #define E1000_TIPG_IPGT_MASK 0x000003FF
598 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
599 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
600 
601 #define DEFAULT_82542_TIPG_IPGR1 2
602 #define DEFAULT_82543_TIPG_IPGR1 8
603 #define E1000_TIPG_IPGR1_SHIFT 10
604 
605 #define DEFAULT_82542_TIPG_IPGR2 10
606 #define DEFAULT_82543_TIPG_IPGR2 6
607 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
608 #define E1000_TIPG_IPGR2_SHIFT 20
609 
610 /* Ethertype field values */
611 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
612 
613 #define ETHERNET_FCS_SIZE 4
614 #define MAX_JUMBO_FRAME_SIZE 0x3F00
615 
616 /* Extended Configuration Control and Size */
617 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
618 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
619 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
620 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
621 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
622 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
623 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
624 
625 #define E1000_PHY_CTRL_SPD_EN 0x00000001
626 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
627 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
628 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
629 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
630 
631 #define E1000_KABGTXD_BGSQLBIAS 0x00050000
632 
633 /* PBA constants */
634 #define E1000_PBA_8K 0x0008 /* 8KB */
635 #define E1000_PBA_12K 0x000C /* 12KB */
636 #define E1000_PBA_16K 0x0010 /* 16KB */
637 #define E1000_PBA_20K 0x0014
638 #define E1000_PBA_22K 0x0016
639 #define E1000_PBA_24K 0x0018
640 #define E1000_PBA_30K 0x001E
641 #define E1000_PBA_32K 0x0020
642 #define E1000_PBA_34K 0x0022
643 #define E1000_PBA_38K 0x0026
644 #define E1000_PBA_40K 0x0028
645 #define E1000_PBA_48K 0x0030 /* 48KB */
646 #define E1000_PBA_64K 0x0040 /* 64KB */
647 
648 #define E1000_PBS_16K E1000_PBA_16K
649 #define E1000_PBS_24K E1000_PBA_24K
650 
651 #define IFS_MAX 80
652 #define IFS_MIN 40
653 #define IFS_RATIO 4
654 #define IFS_STEP 10
655 #define MIN_NUM_XMITS 1000
656 
657 /* SW Semaphore Register */
658 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
659 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
660 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
661 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
662 
663 /* Interrupt Cause Read */
664 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
665 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
666 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
667 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
668 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
669 #define E1000_ICR_RXO 0x00000040 /* rx overrun */
670 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
671 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
672 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
673 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
674 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
675 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
676 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
677 #define E1000_ICR_TXD_LOW 0x00008000
678 #define E1000_ICR_SRPD 0x00010000
679 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
680 #define E1000_ICR_MNG 0x00040000 /* Manageability event */
681 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
682 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
683 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
684 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
685 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
686 #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
687 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
688 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
689 #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
690 #define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
691 #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
692 #define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
693 
694 /* Extended Interrupt Cause Read */
695 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
696 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
697 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
698 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
699 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
700 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
701 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
702 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
703 #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
704 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
705 /* TCP Timer */
706 #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
707 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
708 #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
709 #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
710 
711 /*
712  * This defines the bits that are set in the Interrupt Mask
713  * Set/Read Register. Each bit is documented below:
714  * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
715  * o RXSEQ = Receive Sequence Error
716  */
717 #define POLL_IMS_ENABLE_MASK ( \
718  E1000_IMS_RXDMT0 | \
719  E1000_IMS_RXSEQ)
720 
721 /*
722  * This defines the bits that are set in the Interrupt Mask
723  * Set/Read Register. Each bit is documented below:
724  * o RXT0 = Receiver Timer Interrupt (ring 0)
725  * o TXDW = Transmit Descriptor Written Back
726  * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
727  * o RXSEQ = Receive Sequence Error
728  * o LSC = Link Status Change
729  */
730 #define IMS_ENABLE_MASK ( \
731  E1000_IMS_RXT0 | \
732  E1000_IMS_TXDW | \
733  E1000_IMS_RXDMT0 | \
734  E1000_IMS_RXSEQ | \
735  E1000_IMS_LSC)
736 
737 /* Interrupt Mask Set */
738 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
739 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
740 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
741 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
742 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
743 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
744 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
745 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
746 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
747 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
748 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
749 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
750 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
751 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
752 #define E1000_IMS_SRPD E1000_ICR_SRPD
753 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
754 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
755 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
756 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
757 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
758 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
759 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
760 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
761 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
762 #define E1000_IMS_DSW E1000_ICR_DSW
763 #define E1000_IMS_PHYINT E1000_ICR_PHYINT
764 #define E1000_IMS_EPRST E1000_ICR_EPRST
765 
766 /* Extended Interrupt Mask Set */
767 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
768 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
769 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
770 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
771 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
772 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
773 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
774 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
775 #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
776 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
777 
778 /* Interrupt Cause Set */
779 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
780 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
781 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
782 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
783 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
784 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
785 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
786 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
787 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
788 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
789 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
790 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
791 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
792 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
793 #define E1000_ICS_SRPD E1000_ICR_SRPD
794 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
795 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
796 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
797 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
798 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
799 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
800 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
801 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
802 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
803 #define E1000_ICS_DSW E1000_ICR_DSW
804 #define E1000_ICS_PHYINT E1000_ICR_PHYINT
805 #define E1000_ICS_EPRST E1000_ICR_EPRST
806 
807 /* Extended Interrupt Cause Set */
808 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
809 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
810 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
811 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
812 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
813 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
814 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
815 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
816 #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
817 #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
818 
819 /* Transmit Descriptor Control */
820 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
821 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
822 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
823 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
824 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
825 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
826 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
827 /* Enable the counting of descriptors still to be processed. */
828 #define E1000_TXDCTL_COUNT_DESC 0x00400000
829 
830 /* Flow Control Constants */
831 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
832 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
833 #define FLOW_CONTROL_TYPE 0x8808
834 
835 /* 802.1q VLAN Packet Size */
836 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
837 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
838 
839 /* Receive Address */
840 /*
841  * Number of high/low register pairs in the RAR. The RAR (Receive Address
842  * Registers) holds the directed and multicast addresses that we monitor.
843  * Technically, we have 16 spots. However, we reserve one of these spots
844  * (RAR[15]) for our directed address used by controllers with
845  * manageability enabled, allowing us room for 15 multicast addresses.
846  */
847 #define E1000_RAR_ENTRIES 15
848 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
849 
850 /* Error Codes */
851 #define E1000_SUCCESS 0
852 #define E1000_ERR_NVM 1
853 #define E1000_ERR_PHY 2
854 #define E1000_ERR_CONFIG 3
855 #define E1000_ERR_PARAM 4
856 #define E1000_ERR_MAC_INIT 5
857 #define E1000_ERR_PHY_TYPE 6
858 #define E1000_ERR_RESET 9
859 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
860 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
861 #define E1000_BLK_PHY_RESET 12
862 #define E1000_ERR_SWFW_SYNC 13
863 #define E1000_NOT_IMPLEMENTED 14
864 
865 /* Loop limit on how long we wait for auto-negotiation to complete */
866 #define FIBER_LINK_UP_LIMIT 50
867 #define COPPER_LINK_UP_LIMIT 10
868 #define PHY_AUTO_NEG_LIMIT 45
869 #define PHY_FORCE_LIMIT 20
870 /* Number of 100 microseconds we wait for PCI Express master disable */
871 #define MASTER_DISABLE_TIMEOUT 800
872 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
873 #define PHY_CFG_TIMEOUT 100
874 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
875 #define MDIO_OWNERSHIP_TIMEOUT 10
876 /* Number of milliseconds for NVM auto read done after MAC reset. */
877 #define AUTO_READ_DONE_TIMEOUT 10
878 
879 /* Flow Control */
880 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
881 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
882 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
883 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
884 
885 /* Transmit Configuration Word */
886 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
887 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
888 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
889 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
890 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
891 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
892 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */
893 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
894 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
895 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
896 
897 /* Receive Configuration Word */
898 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
899 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
900 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
901 #define E1000_RXCW_CC 0x10000000 /* Receive config change */
902 #define E1000_RXCW_C 0x20000000 /* Receive config */
903 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
904 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
905 
906 /* PCI Express Control */
907 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
908 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
909 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
910 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
911 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
912 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
913 
914 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
915  E1000_GCR_RXDSCW_NO_SNOOP | \
916  E1000_GCR_RXDSCR_NO_SNOOP | \
917  E1000_GCR_TXD_NO_SNOOP | \
918  E1000_GCR_TXDSCW_NO_SNOOP | \
919  E1000_GCR_TXDSCR_NO_SNOOP)
920 
921 /* PHY Control Register */
922 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
923 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
924 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
925 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
926 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
927 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
928 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
929 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
930 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
931 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
932 #define MII_CR_SPEED_1000 0x0040
933 #define MII_CR_SPEED_100 0x2000
934 #define MII_CR_SPEED_10 0x0000
935 
936 /* PHY Status Register */
937 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
938 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
939 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
940 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
941 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
942 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
943 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
944 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
945 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
946 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
947 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
948 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
949 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
950 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
951 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
952 
953 /* Autoneg Advertisement Register */
954 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
955 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
956 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
957 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
958 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
959 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
960 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
961 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
962 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
963 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
964 
965 /* Link Partner Ability Register (Base Page) */
966 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
967 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
968 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
969 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
970 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
971 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
972 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
973 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
974 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
975 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
976 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
977 
978 /* Autoneg Expansion Register */
979 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
980 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
981 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
982 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
983 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
984 
985 /* 1000BASE-T Control Register */
986 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
987 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
988 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
989 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
990  /* 0=DTE device */
991 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
992  /* 0=Configure PHY as Slave */
993 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
994  /* 0=Automatic Master/Slave config */
995 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
996 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
997 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
998 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
999 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
1000 
1001 /* 1000BASE-T Status Register */
1002 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
1003 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
1004 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1005 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1006 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1007 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1008 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */
1009 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1010 
1011 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1012 
1013 /* PHY 1000 MII Register/Bit Definitions */
1014 /* PHY Registers defined by IEEE */
1015 #define PHY_CONTROL 0x00 /* Control Register */
1016 #define PHY_STATUS 0x01 /* Status Regiser */
1017 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1018 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1019 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1020 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1021 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1022 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1023 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1024 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1025 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1026 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1027 
1028 /* NVM Control */
1029 #define E1000_EECD_SK 0x00000001 /* NVM Clock */
1030 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1031 #define E1000_EECD_DI 0x00000004 /* NVM Data In */
1032 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1033 #define E1000_EECD_FWE_MASK 0x00000030
1034 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1035 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1036 #define E1000_EECD_FWE_SHIFT 4
1037 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1038 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1039 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
1040 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1041 /* NVM Addressing bits based on type 0=small, 1=large */
1042 #define E1000_EECD_ADDR_BITS 0x00000400
1043 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1044 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
1045 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1046 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1047 #define E1000_EECD_SIZE_EX_SHIFT 11
1048 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1049 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1050 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1051 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1052 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1053 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1054 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1055 #define E1000_EECD_SECVAL_SHIFT 22
1056 
1057 #define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */
1058 #define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */
1059 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */
1060 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1061 #define E1000_NVM_RW_REG_START 1 /* Start operation */
1062 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1063 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1064 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
1065 #define E1000_FLASH_UPDATES 2000
1066 
1067 /* NVM Word Offsets */
1068 #define NVM_COMPAT 0x0003
1069 #define NVM_ID_LED_SETTINGS 0x0004
1070 #define NVM_VERSION 0x0005
1071 #define NVM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
1072 #define NVM_PHY_CLASS_WORD 0x0007
1073 #define NVM_INIT_CONTROL1_REG 0x000A
1074 #define NVM_INIT_CONTROL2_REG 0x000F
1075 #define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
1076 #define NVM_INIT_CONTROL3_PORT_B 0x0014
1077 #define NVM_INIT_3GIO_3 0x001A
1078 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1079 #define NVM_INIT_CONTROL3_PORT_A 0x0024
1080 #define NVM_CFG 0x0012
1081 #define NVM_FLASH_VERSION 0x0032
1082 #define NVM_ALT_MAC_ADDR_PTR 0x0037
1083 #define NVM_CHECKSUM_REG 0x003F
1084 
1085 #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
1086 #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
1087 
1088 /* Mask bits for fields in Word 0x0f of the NVM */
1089 #define NVM_WORD0F_PAUSE_MASK 0x3000
1090 #define NVM_WORD0F_PAUSE 0x1000
1091 #define NVM_WORD0F_ASM_DIR 0x2000
1092 #define NVM_WORD0F_ANE 0x0800
1093 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
1094 #define NVM_WORD0F_LPLU 0x0001
1095 
1096 /* Mask bits for fields in Word 0x1a of the NVM */
1097 #define NVM_WORD1A_ASPM_MASK 0x000C
1098 
1099 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1100 #define NVM_SUM 0xBABA
1101 
1102 #define NVM_MAC_ADDR_OFFSET 0
1103 #define NVM_PBA_OFFSET_0 8
1104 #define NVM_PBA_OFFSET_1 9
1105 #define NVM_RESERVED_WORD 0xFFFF
1106 #define NVM_PHY_CLASS_A 0x8000
1107 #define NVM_SERDES_AMPLITUDE_MASK 0x000F
1108 #define NVM_SIZE_MASK 0x1C00
1109 #define NVM_SIZE_SHIFT 10
1110 #define NVM_WORD_SIZE_BASE_SHIFT 6
1111 #define NVM_SWDPIO_EXT_SHIFT 4
1112 
1113 /* NVM Commands - Microwire */
1114 #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */
1115 #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */
1116 #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */
1117 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1118 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erast/write disable */
1119 
1120 /* NVM Commands - SPI */
1121 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1122 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
1123 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
1124 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1125 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1126 #define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */
1127 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
1128 #define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */
1129 
1130 /* SPI NVM Status Register */
1131 #define NVM_STATUS_RDY_SPI 0x01
1132 #define NVM_STATUS_WEN_SPI 0x02
1133 #define NVM_STATUS_BP0_SPI 0x04
1134 #define NVM_STATUS_BP1_SPI 0x08
1135 #define NVM_STATUS_WPEN_SPI 0x80
1136 
1137 /* Word definitions for ID LED Settings */
1138 #define ID_LED_RESERVED_0000 0x0000
1139 #define ID_LED_RESERVED_FFFF 0xFFFF
1140 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1141  (ID_LED_OFF1_OFF2 << 8) | \
1142  (ID_LED_DEF1_DEF2 << 4) | \
1143  (ID_LED_DEF1_DEF2))
1144 #define ID_LED_DEF1_DEF2 0x1
1145 #define ID_LED_DEF1_ON2 0x2
1146 #define ID_LED_DEF1_OFF2 0x3
1147 #define ID_LED_ON1_DEF2 0x4
1148 #define ID_LED_ON1_ON2 0x5
1149 #define ID_LED_ON1_OFF2 0x6
1150 #define ID_LED_OFF1_DEF2 0x7
1151 #define ID_LED_OFF1_ON2 0x8
1152 #define ID_LED_OFF1_OFF2 0x9
1153 
1154 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1155 #define IGP_ACTIVITY_LED_ENABLE 0x0300
1156 #define IGP_LED3_MODE 0x07000000
1157 
1158 /* PCI/PCI-X/PCI-EX Config space */
1159 #define PCIX_COMMAND_REGISTER 0xE6
1160 #define PCIX_STATUS_REGISTER_LO 0xE8
1161 #define PCIX_STATUS_REGISTER_HI 0xEA
1162 #define PCI_HEADER_TYPE_REGISTER 0x0E
1163 #define PCIE_LINK_STATUS 0x12
1164 
1165 #define PCIX_COMMAND_MMRBC_MASK 0x000C
1166 #define PCIX_COMMAND_MMRBC_SHIFT 0x2
1167 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1168 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1169 #define PCIX_STATUS_HI_MMRBC_4K 0x3
1170 #define PCIX_STATUS_HI_MMRBC_2K 0x2
1171 #define PCIX_STATUS_LO_FUNC_MASK 0x7
1172 #define PCI_HEADER_TYPE_MULTIFUNC 0x80
1173 #define PCIE_LINK_WIDTH_MASK 0x3F0
1174 #define PCIE_LINK_WIDTH_SHIFT 4
1175 
1176 #ifndef ETH_ADDR_LEN
1177 #define ETH_ADDR_LEN 6
1178 #endif
1179 
1180 #define PHY_REVISION_MASK 0xFFFFFFF0
1181 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1182 #define MAX_PHY_MULTI_PAGE_REG 0xF
1183 
1184 /* Bit definitions for valid PHY IDs. */
1185 /*
1186  * I = Integrated
1187  * E = External
1188  */
1189 #define M88E1000_E_PHY_ID 0x01410C50
1190 #define M88E1000_I_PHY_ID 0x01410C30
1191 #define M88E1011_I_PHY_ID 0x01410C20
1192 #define IGP01E1000_I_PHY_ID 0x02A80380
1193 #define M88E1011_I_REV_4 0x04
1194 #define M88E1111_I_PHY_ID 0x01410CC0
1195 #define GG82563_E_PHY_ID 0x01410CA0
1196 #define IGP03E1000_E_PHY_ID 0x02A80390
1197 #define IFE_E_PHY_ID 0x02A80330
1198 #define IFE_PLUS_E_PHY_ID 0x02A80320
1199 #define IFE_C_E_PHY_ID 0x02A80310
1200 #define M88_VENDOR 0x0141
1201 
1202 /* M88E1000 Specific Registers */
1203 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1204 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1205 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1206 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1207 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1208 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1209 
1210 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1211 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
1212 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1213 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1214 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1215 
1216 /* M88E1000 PHY Specific Control Register */
1217 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1218 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
1219 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1220 /* 1=CLK125 low, 0=CLK125 toggling */
1221 #define M88E1000_PSCR_CLK125_DISABLE 0x0010
1222 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1223  /* Manual MDI configuration */
1224 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1225 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1226 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
1227 /* Auto crossover enabled all speeds */
1228 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
1229 /*
1230  * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
1231  * 0=Normal 10BASE-T Rx Threshold
1232  */
1233 #define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
1234 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
1235 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1236 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1237 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1238 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
1239 
1240 /* M88E1000 PHY Specific Status Register */
1241 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1242 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1243 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1244 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1245 /*
1246  * 0 = <50M
1247  * 1 = 50-80M
1248  * 2 = 80-110M
1249  * 3 = 110-140M
1250  * 4 = >140M
1251  */
1252 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
1253 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1254 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1255 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1256 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1257 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1258 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1259 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1260 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1261 
1262 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1263 
1264 /* M88E1000 Extended PHY Specific Control Register */
1265 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1266 /*
1267  * 1 = Lost lock detect enabled.
1268  * Will assert lost lock and bring
1269  * link down if idle not seen
1270  * within 1ms in 1000BASE-T
1271  */
1272 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
1273 /*
1274  * Number of times we will attempt to autonegotiate before downshifting if we
1275  * are the master
1276  */
1277 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1278 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1279 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1280 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1281 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1282 /*
1283  * Number of times we will attempt to autonegotiate before downshifting if we
1284  * are the slave
1285  */
1286 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1287 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1288 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1289 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1290 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
1291 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
1292 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1293 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
1294 
1295 /* M88EC018 Rev 2 specific DownShift settings */
1296 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1297 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
1298 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
1299 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
1300 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
1301 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1302 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
1303 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
1304 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
1305 
1306 /*
1307  * Bits...
1308  * 15-5: page
1309  * 4-0: register offset
1310  */
1311 #define GG82563_PAGE_SHIFT 5
1312 #define GG82563_REG(page, reg) \
1313  (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1314 #define GG82563_MIN_ALT_REG 30
1315 
1316 /* GG82563 Specific Registers */
1317 #define GG82563_PHY_SPEC_CTRL \
1318  GG82563_REG(0, 16) /* PHY Specific Control */
1319 #define GG82563_PHY_SPEC_STATUS \
1320  GG82563_REG(0, 17) /* PHY Specific Status */
1321 #define GG82563_PHY_INT_ENABLE \
1322  GG82563_REG(0, 18) /* Interrupt Enable */
1323 #define GG82563_PHY_SPEC_STATUS_2 \
1324  GG82563_REG(0, 19) /* PHY Specific Status 2 */
1325 #define GG82563_PHY_RX_ERR_CNTR \
1326  GG82563_REG(0, 21) /* Receive Error Counter */
1327 #define GG82563_PHY_PAGE_SELECT \
1328  GG82563_REG(0, 22) /* Page Select */
1329 #define GG82563_PHY_SPEC_CTRL_2 \
1330  GG82563_REG(0, 26) /* PHY Specific Control 2 */
1331 #define GG82563_PHY_PAGE_SELECT_ALT \
1332  GG82563_REG(0, 29) /* Alternate Page Select */
1333 #define GG82563_PHY_TEST_CLK_CTRL \
1334  GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
1335 
1336 #define GG82563_PHY_MAC_SPEC_CTRL \
1337  GG82563_REG(2, 21) /* MAC Specific Control Register */
1338 #define GG82563_PHY_MAC_SPEC_CTRL_2 \
1339  GG82563_REG(2, 26) /* MAC Specific Control 2 */
1340 
1341 #define GG82563_PHY_DSP_DISTANCE \
1342  GG82563_REG(5, 26) /* DSP Distance */
1343 
1344 /* Page 193 - Port Control Registers */
1345 #define GG82563_PHY_KMRN_MODE_CTRL \
1346  GG82563_REG(193, 16) /* Kumeran Mode Control */
1347 #define GG82563_PHY_PORT_RESET \
1348  GG82563_REG(193, 17) /* Port Reset */
1349 #define GG82563_PHY_REVISION_ID \
1350  GG82563_REG(193, 18) /* Revision ID */
1351 #define GG82563_PHY_DEVICE_ID \
1352  GG82563_REG(193, 19) /* Device ID */
1353 #define GG82563_PHY_PWR_MGMT_CTRL \
1354  GG82563_REG(193, 20) /* Power Management Control */
1355 #define GG82563_PHY_RATE_ADAPT_CTRL \
1356  GG82563_REG(193, 25) /* Rate Adaptation Control */
1357 
1358 /* Page 194 - KMRN Registers */
1359 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
1360  GG82563_REG(194, 16) /* FIFO's Control/Status */
1361 #define GG82563_PHY_KMRN_CTRL \
1362  GG82563_REG(194, 17) /* Control */
1363 #define GG82563_PHY_INBAND_CTRL \
1364  GG82563_REG(194, 18) /* Inband Control */
1365 #define GG82563_PHY_KMRN_DIAGNOSTIC \
1366  GG82563_REG(194, 19) /* Diagnostic */
1367 #define GG82563_PHY_ACK_TIMEOUTS \
1368  GG82563_REG(194, 20) /* Acknowledge Timeouts */
1369 #define GG82563_PHY_ADV_ABILITY \
1370  GG82563_REG(194, 21) /* Advertised Ability */
1371 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
1372  GG82563_REG(194, 23) /* Link Partner Advertised Ability */
1373 #define GG82563_PHY_ADV_NEXT_PAGE \
1374  GG82563_REG(194, 24) /* Advertised Next Page */
1375 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
1376  GG82563_REG(194, 25) /* Link Partner Advertised Next page */
1377 #define GG82563_PHY_KMRN_MISC \
1378  GG82563_REG(194, 26) /* Misc. */
1379 
1380 /* MDI Control */
1381 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1382 #define E1000_MDIC_REG_MASK 0x001F0000
1383 #define E1000_MDIC_REG_SHIFT 16
1384 #define E1000_MDIC_PHY_MASK 0x03E00000
1385 #define E1000_MDIC_PHY_SHIFT 21
1386 #define E1000_MDIC_OP_WRITE 0x04000000
1387 #define E1000_MDIC_OP_READ 0x08000000
1388 #define E1000_MDIC_READY 0x10000000
1389 #define E1000_MDIC_INT_EN 0x20000000
1390 #define E1000_MDIC_ERROR 0x40000000
1391 
1392 /* SerDes Control */
1393 #define E1000_GEN_CTL_READY 0x80000000
1394 #define E1000_GEN_CTL_ADDRESS_SHIFT 8
1395 #define E1000_GEN_POLL_TIMEOUT 640
1396 
1397 #endif