Xenomai  3.0.8
e1000_hw.h
1 /*******************************************************************************
2 
3  Intel PRO/1000 Linux driver
4  Copyright(c) 1999 - 2008 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Contact Information:
23  Linux NICS <linux.nics@intel.com>
24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #ifndef _E1000_HW_H_
30 #define _E1000_HW_H_
31 
32 #include "e1000_osdep.h"
33 #include "e1000_regs.h"
34 #include "e1000_defines.h"
35 
36 struct e1000_hw;
37 
38 #define E1000_DEV_ID_82542 0x1000
39 #define E1000_DEV_ID_82543GC_FIBER 0x1001
40 #define E1000_DEV_ID_82543GC_COPPER 0x1004
41 #define E1000_DEV_ID_82544EI_COPPER 0x1008
42 #define E1000_DEV_ID_82544EI_FIBER 0x1009
43 #define E1000_DEV_ID_82544GC_COPPER 0x100C
44 #define E1000_DEV_ID_82544GC_LOM 0x100D
45 #define E1000_DEV_ID_82540EM 0x100E
46 #define E1000_DEV_ID_82540EM_LOM 0x1015
47 #define E1000_DEV_ID_82540EP_LOM 0x1016
48 #define E1000_DEV_ID_82540EP 0x1017
49 #define E1000_DEV_ID_82540EP_LP 0x101E
50 #define E1000_DEV_ID_82545EM_COPPER 0x100F
51 #define E1000_DEV_ID_82545EM_FIBER 0x1011
52 #define E1000_DEV_ID_82545GM_COPPER 0x1026
53 #define E1000_DEV_ID_82545GM_FIBER 0x1027
54 #define E1000_DEV_ID_82545GM_SERDES 0x1028
55 #define E1000_DEV_ID_82546EB_COPPER 0x1010
56 #define E1000_DEV_ID_82546EB_FIBER 0x1012
57 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
58 #define E1000_DEV_ID_82546GB_COPPER 0x1079
59 #define E1000_DEV_ID_82546GB_FIBER 0x107A
60 #define E1000_DEV_ID_82546GB_SERDES 0x107B
61 #define E1000_DEV_ID_82546GB_PCIE 0x108A
62 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
63 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
64 #define E1000_DEV_ID_82541EI 0x1013
65 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
66 #define E1000_DEV_ID_82541ER_LOM 0x1014
67 #define E1000_DEV_ID_82541ER 0x1078
68 #define E1000_DEV_ID_82541GI 0x1076
69 #define E1000_DEV_ID_82541GI_LF 0x107C
70 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
71 #define E1000_DEV_ID_82547EI 0x1019
72 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
73 #define E1000_DEV_ID_82547GI 0x1075
74 #define E1000_DEV_ID_82571EB_COPPER 0x105E
75 #define E1000_DEV_ID_82571EB_FIBER 0x105F
76 #define E1000_DEV_ID_82571EB_SERDES 0x1060
77 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
78 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
79 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
80 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
81 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
82 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
83 #define E1000_DEV_ID_82572EI_COPPER 0x107D
84 #define E1000_DEV_ID_82572EI_FIBER 0x107E
85 #define E1000_DEV_ID_82572EI_SERDES 0x107F
86 #define E1000_DEV_ID_82572EI 0x10B9
87 #define E1000_DEV_ID_82573E 0x108B
88 #define E1000_DEV_ID_82573E_IAMT 0x108C
89 #define E1000_DEV_ID_82573L 0x109A
90 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
91 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
92 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
93 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
94 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
95 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
96 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
97 #define E1000_DEV_ID_ICH8_IFE 0x104C
98 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
99 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
100 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
101 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
102 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
103 #define E1000_DEV_ID_ICH9_IFE 0x10C0
104 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
105 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
106 
107 #define E1000_REVISION_0 0
108 #define E1000_REVISION_1 1
109 #define E1000_REVISION_2 2
110 #define E1000_REVISION_3 3
111 #define E1000_REVISION_4 4
112 
113 #define E1000_FUNC_0 0
114 #define E1000_FUNC_1 1
115 
116 typedef enum {
117  e1000_undefined = 0,
118  e1000_82542,
119  e1000_82543,
120  e1000_82544,
121  e1000_82540,
122  e1000_82545,
123  e1000_82545_rev_3,
124  e1000_82546,
125  e1000_82546_rev_3,
126  e1000_82541,
127  e1000_82541_rev_2,
128  e1000_82547,
129  e1000_82547_rev_2,
130  e1000_82571,
131  e1000_82572,
132  e1000_82573,
133  e1000_80003es2lan,
134  e1000_ich8lan,
135  e1000_ich9lan,
136  e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
137 } e1000_mac_type;
138 
139 typedef enum {
140  e1000_media_type_unknown = 0,
141  e1000_media_type_copper = 1,
142  e1000_media_type_fiber = 2,
143  e1000_media_type_internal_serdes = 3,
144  e1000_num_media_types
145 } e1000_media_type;
146 
147 typedef enum {
148  e1000_nvm_unknown = 0,
149  e1000_nvm_none,
150  e1000_nvm_eeprom_spi,
151  e1000_nvm_eeprom_microwire,
152  e1000_nvm_flash_hw,
153  e1000_nvm_flash_sw
154 } e1000_nvm_type;
155 
156 typedef enum {
157  e1000_nvm_override_none = 0,
158  e1000_nvm_override_spi_small,
159  e1000_nvm_override_spi_large,
160  e1000_nvm_override_microwire_small,
161  e1000_nvm_override_microwire_large
162 } e1000_nvm_override;
163 
164 typedef enum {
165  e1000_phy_unknown = 0,
166  e1000_phy_none,
167  e1000_phy_m88,
168  e1000_phy_igp,
169  e1000_phy_igp_2,
170  e1000_phy_gg82563,
171  e1000_phy_igp_3,
172  e1000_phy_ife,
173 } e1000_phy_type;
174 
175 typedef enum {
176  e1000_bus_type_unknown = 0,
177  e1000_bus_type_pci,
178  e1000_bus_type_pcix,
179  e1000_bus_type_pci_express,
180  e1000_bus_type_reserved
181 } e1000_bus_type;
182 
183 typedef enum {
184  e1000_bus_speed_unknown = 0,
185  e1000_bus_speed_33,
186  e1000_bus_speed_66,
187  e1000_bus_speed_100,
188  e1000_bus_speed_120,
189  e1000_bus_speed_133,
190  e1000_bus_speed_2500,
191  e1000_bus_speed_5000,
192  e1000_bus_speed_reserved
193 } e1000_bus_speed;
194 
195 typedef enum {
196  e1000_bus_width_unknown = 0,
197  e1000_bus_width_pcie_x1,
198  e1000_bus_width_pcie_x2,
199  e1000_bus_width_pcie_x4 = 4,
200  e1000_bus_width_pcie_x8 = 8,
201  e1000_bus_width_32,
202  e1000_bus_width_64,
203  e1000_bus_width_reserved
204 } e1000_bus_width;
205 
206 typedef enum {
207  e1000_1000t_rx_status_not_ok = 0,
208  e1000_1000t_rx_status_ok,
209  e1000_1000t_rx_status_undefined = 0xFF
210 } e1000_1000t_rx_status;
211 
212 typedef enum {
213  e1000_rev_polarity_normal = 0,
214  e1000_rev_polarity_reversed,
215  e1000_rev_polarity_undefined = 0xFF
216 } e1000_rev_polarity;
217 
218 typedef enum {
219  e1000_fc_none = 0,
220  e1000_fc_rx_pause,
221  e1000_fc_tx_pause,
222  e1000_fc_full,
223  e1000_fc_default = 0xFF
224 } e1000_fc_type;
225 
226 typedef enum {
227  e1000_ffe_config_enabled = 0,
228  e1000_ffe_config_active,
229  e1000_ffe_config_blocked
230 } e1000_ffe_config;
231 
232 typedef enum {
233  e1000_dsp_config_disabled = 0,
234  e1000_dsp_config_enabled,
235  e1000_dsp_config_activated,
236  e1000_dsp_config_undefined = 0xFF
237 } e1000_dsp_config;
238 
239 /* Receive Descriptor */
240 struct e1000_rx_desc {
241  u64 buffer_addr; /* Address of the descriptor's data buffer */
242  u16 length; /* Length of data DMAed into data buffer */
243  u16 csum; /* Packet checksum */
244  u8 status; /* Descriptor status */
245  u8 errors; /* Descriptor Errors */
246  u16 special;
247 };
248 
249 /* Receive Descriptor - Extended */
250 union e1000_rx_desc_extended {
251  struct {
252  u64 buffer_addr;
253  u64 reserved;
254  } read;
255  struct {
256  struct {
257  u32 mrq; /* Multiple Rx Queues */
258  union {
259  u32 rss; /* RSS Hash */
260  struct {
261  u16 ip_id; /* IP id */
262  u16 csum; /* Packet Checksum */
263  } csum_ip;
264  } hi_dword;
265  } lower;
266  struct {
267  u32 status_error; /* ext status/error */
268  u16 length;
269  u16 vlan; /* VLAN tag */
270  } upper;
271  } wb; /* writeback */
272 };
273 
274 #define MAX_PS_BUFFERS 4
275 /* Receive Descriptor - Packet Split */
276 union e1000_rx_desc_packet_split {
277  struct {
278  /* one buffer for protocol header(s), three data buffers */
279  u64 buffer_addr[MAX_PS_BUFFERS];
280  } read;
281  struct {
282  struct {
283  u32 mrq; /* Multiple Rx Queues */
284  union {
285  u32 rss; /* RSS Hash */
286  struct {
287  u16 ip_id; /* IP id */
288  u16 csum; /* Packet Checksum */
289  } csum_ip;
290  } hi_dword;
291  } lower;
292  struct {
293  u32 status_error; /* ext status/error */
294  u16 length0; /* length of buffer 0 */
295  u16 vlan; /* VLAN tag */
296  } middle;
297  struct {
298  u16 header_status;
299  u16 length[3]; /* length of buffers 1-3 */
300  } upper;
301  u64 reserved;
302  } wb; /* writeback */
303 };
304 
305 /* Transmit Descriptor */
306 struct e1000_tx_desc {
307  u64 buffer_addr; /* Address of the descriptor's data buffer */
308  union {
309  u32 data;
310  struct {
311  u16 length; /* Data buffer length */
312  u8 cso; /* Checksum offset */
313  u8 cmd; /* Descriptor control */
314  } flags;
315  } lower;
316  union {
317  u32 data;
318  struct {
319  u8 status; /* Descriptor status */
320  u8 css; /* Checksum start */
321  u16 special;
322  } fields;
323  } upper;
324 };
325 
326 /* Offload Context Descriptor */
327 struct e1000_context_desc {
328  union {
329  u32 ip_config;
330  struct {
331  u8 ipcss; /* IP checksum start */
332  u8 ipcso; /* IP checksum offset */
333  u16 ipcse; /* IP checksum end */
334  } ip_fields;
335  } lower_setup;
336  union {
337  u32 tcp_config;
338  struct {
339  u8 tucss; /* TCP checksum start */
340  u8 tucso; /* TCP checksum offset */
341  u16 tucse; /* TCP checksum end */
342  } tcp_fields;
343  } upper_setup;
344  u32 cmd_and_length;
345  union {
346  u32 data;
347  struct {
348  u8 status; /* Descriptor status */
349  u8 hdr_len; /* Header length */
350  u16 mss; /* Maximum segment size */
351  } fields;
352  } tcp_seg_setup;
353 };
354 
355 /* Offload data descriptor */
356 struct e1000_data_desc {
357  u64 buffer_addr; /* Address of the descriptor's buffer address */
358  union {
359  u32 data;
360  struct {
361  u16 length; /* Data buffer length */
362  u8 typ_len_ext;
363  u8 cmd;
364  } flags;
365  } lower;
366  union {
367  u32 data;
368  struct {
369  u8 status; /* Descriptor status */
370  u8 popts; /* Packet Options */
371  u16 special;
372  } fields;
373  } upper;
374 };
375 
376 /* Statistics counters collected by the MAC */
377 struct e1000_hw_stats {
378  u64 crcerrs;
379  u64 algnerrc;
380  u64 symerrs;
381  u64 rxerrc;
382  u64 mpc;
383  u64 scc;
384  u64 ecol;
385  u64 mcc;
386  u64 latecol;
387  u64 colc;
388  u64 dc;
389  u64 tncrs;
390  u64 sec;
391  u64 cexterr;
392  u64 rlec;
393  u64 xonrxc;
394  u64 xontxc;
395  u64 xoffrxc;
396  u64 xofftxc;
397  u64 fcruc;
398  u64 prc64;
399  u64 prc127;
400  u64 prc255;
401  u64 prc511;
402  u64 prc1023;
403  u64 prc1522;
404  u64 gprc;
405  u64 bprc;
406  u64 mprc;
407  u64 gptc;
408  u64 gorc;
409  u64 gotc;
410  u64 rnbc;
411  u64 ruc;
412  u64 rfc;
413  u64 roc;
414  u64 rjc;
415  u64 mgprc;
416  u64 mgpdc;
417  u64 mgptc;
418  u64 tor;
419  u64 tot;
420  u64 tpr;
421  u64 tpt;
422  u64 ptc64;
423  u64 ptc127;
424  u64 ptc255;
425  u64 ptc511;
426  u64 ptc1023;
427  u64 ptc1522;
428  u64 mptc;
429  u64 bptc;
430  u64 tsctc;
431  u64 tsctfc;
432  u64 iac;
433  u64 icrxptc;
434  u64 icrxatc;
435  u64 ictxptc;
436  u64 ictxatc;
437  u64 ictxqec;
438  u64 ictxqmtc;
439  u64 icrxdmtc;
440  u64 icrxoc;
441  u64 cbtmpc;
442  u64 htdpmc;
443  u64 cbrdpc;
444  u64 cbrmpc;
445  u64 rpthc;
446  u64 hgptc;
447  u64 htcbdpc;
448  u64 hgorc;
449  u64 hgotc;
450  u64 lenerrs;
451  u64 scvpc;
452  u64 hrmpc;
453 };
454 
455 struct e1000_phy_stats {
456  u32 idle_errors;
457  u32 receive_errors;
458 };
459 
460 struct e1000_host_mng_dhcp_cookie {
461  u32 signature;
462  u8 status;
463  u8 reserved0;
464  u16 vlan_id;
465  u32 reserved1;
466  u16 reserved2;
467  u8 reserved3;
468  u8 checksum;
469 };
470 
471 /* Host Interface "Rev 1" */
472 struct e1000_host_command_header {
473  u8 command_id;
474  u8 command_length;
475  u8 command_options;
476  u8 checksum;
477 };
478 
479 #define E1000_HI_MAX_DATA_LENGTH 252
480 struct e1000_host_command_info {
481  struct e1000_host_command_header command_header;
482  u8 command_data[E1000_HI_MAX_DATA_LENGTH];
483 };
484 
485 /* Host Interface "Rev 2" */
486 struct e1000_host_mng_command_header {
487  u8 command_id;
488  u8 checksum;
489  u16 reserved1;
490  u16 reserved2;
491  u16 command_length;
492 };
493 
494 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
495 struct e1000_host_mng_command_info {
496  struct e1000_host_mng_command_header command_header;
497  u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
498 };
499 
500 #include "e1000_mac.h"
501 #include "e1000_phy.h"
502 #include "e1000_nvm.h"
503 #include "e1000_manage.h"
504 
505 struct e1000_functions {
506  /* Function pointers for the MAC. */
507  s32 (*init_mac_params)(struct e1000_hw *);
508  s32 (*blink_led)(struct e1000_hw *);
509  s32 (*check_for_link)(struct e1000_hw *);
510  bool (*check_mng_mode)(struct e1000_hw *hw);
511  s32 (*cleanup_led)(struct e1000_hw *);
512  void (*clear_hw_cntrs)(struct e1000_hw *);
513  void (*clear_vfta)(struct e1000_hw *);
514  s32 (*get_bus_info)(struct e1000_hw *);
515  s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
516  s32 (*led_on)(struct e1000_hw *);
517  s32 (*led_off)(struct e1000_hw *);
518  void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32,
519  u32);
520  void (*remove_device)(struct e1000_hw *);
521  s32 (*reset_hw)(struct e1000_hw *);
522  s32 (*init_hw)(struct e1000_hw *);
523  s32 (*setup_link)(struct e1000_hw *);
524  s32 (*setup_physical_interface)(struct e1000_hw *);
525  s32 (*setup_led)(struct e1000_hw *);
526  void (*write_vfta)(struct e1000_hw *, u32, u32);
527  void (*mta_set)(struct e1000_hw *, u32);
528  void (*config_collision_dist)(struct e1000_hw*);
529  void (*rar_set)(struct e1000_hw*, u8*, u32);
530  s32 (*read_mac_addr)(struct e1000_hw*);
531  s32 (*validate_mdi_setting)(struct e1000_hw*);
532  s32 (*mng_host_if_write)(struct e1000_hw*, u8*, u16, u16, u8*);
533  s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
534  struct e1000_host_mng_command_header*);
535  s32 (*mng_enable_host_if)(struct e1000_hw*);
536  s32 (*wait_autoneg)(struct e1000_hw*);
537 
538  /* Function pointers for the PHY. */
539  s32 (*init_phy_params)(struct e1000_hw *);
540  s32 (*acquire_phy)(struct e1000_hw *);
541  s32 (*check_polarity)(struct e1000_hw *);
542  s32 (*check_reset_block)(struct e1000_hw *);
543  s32 (*commit_phy)(struct e1000_hw *);
544  s32 (*force_speed_duplex)(struct e1000_hw *);
545  s32 (*get_cfg_done)(struct e1000_hw *hw);
546  s32 (*get_cable_length)(struct e1000_hw *);
547  s32 (*get_phy_info)(struct e1000_hw *);
548  s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
549  void (*release_phy)(struct e1000_hw *);
550  s32 (*reset_phy)(struct e1000_hw *);
551  s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
552  s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
553  s32 (*write_phy_reg)(struct e1000_hw *, u32, u16);
554  void (*power_up_phy)(struct e1000_hw *);
555  void (*power_down_phy)(struct e1000_hw *);
556 
557  /* Function pointers for the NVM. */
558  s32 (*init_nvm_params)(struct e1000_hw *);
559  s32 (*acquire_nvm)(struct e1000_hw *);
560  s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
561  void (*release_nvm)(struct e1000_hw *);
562  void (*reload_nvm)(struct e1000_hw *);
563  s32 (*update_nvm)(struct e1000_hw *);
564  s32 (*valid_led_default)(struct e1000_hw *, u16 *);
565  s32 (*validate_nvm)(struct e1000_hw *);
566  s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
567 };
568 
569 struct e1000_mac_info {
570  u8 addr[6];
571  u8 perm_addr[6];
572 
573  e1000_mac_type type;
574 
575  u32 collision_delta;
576  u32 ledctl_default;
577  u32 ledctl_mode1;
578  u32 ledctl_mode2;
579  u32 mc_filter_type;
580  u32 tx_packet_delta;
581  u32 txcw;
582 
583  u16 current_ifs_val;
584  u16 ifs_max_val;
585  u16 ifs_min_val;
586  u16 ifs_ratio;
587  u16 ifs_step_size;
588  u16 mta_reg_count;
589  u16 rar_entry_count;
590 
591  u8 forced_speed_duplex;
592 
593  bool adaptive_ifs;
594  bool arc_subsystem_valid;
595  bool asf_firmware_present;
596  bool autoneg;
597  bool autoneg_failed;
598  bool disable_av;
599  bool disable_hw_init_bits;
600  bool get_link_status;
601  bool ifs_params_forced;
602  bool in_ifs_mode;
603  bool report_tx_early;
604  bool serdes_has_link;
605  bool tx_pkt_filtering;
606 };
607 
608 struct e1000_phy_info {
609  e1000_phy_type type;
610 
611  e1000_1000t_rx_status local_rx;
612  e1000_1000t_rx_status remote_rx;
613  e1000_ms_type ms_type;
614  e1000_ms_type original_ms_type;
615  e1000_rev_polarity cable_polarity;
616  e1000_smart_speed smart_speed;
617 
618  u32 addr;
619  u32 id;
620  u32 reset_delay_us; /* in usec */
621  u32 revision;
622 
623  e1000_media_type media_type;
624 
625  u16 autoneg_advertised;
626  u16 autoneg_mask;
627  u16 cable_length;
628  u16 max_cable_length;
629  u16 min_cable_length;
630 
631  u8 mdix;
632 
633  bool disable_polarity_correction;
634  bool is_mdix;
635  bool polarity_correction;
636  bool reset_disable;
637  bool speed_downgraded;
638  bool autoneg_wait_to_complete;
639 };
640 
641 struct e1000_nvm_info {
642  e1000_nvm_type type;
643  e1000_nvm_override override;
644 
645  u32 flash_bank_size;
646  u32 flash_base_addr;
647 
648  u16 word_size;
649  u16 delay_usec;
650  u16 address_bits;
651  u16 opcode_bits;
652  u16 page_size;
653 };
654 
655 struct e1000_bus_info {
656  e1000_bus_type type;
657  e1000_bus_speed speed;
658  e1000_bus_width width;
659 
660  u32 snoop;
661 
662  u16 func;
663  u16 pci_cmd_word;
664 };
665 
666 struct e1000_fc_info {
667  u32 high_water; /* Flow control high-water mark */
668  u32 low_water; /* Flow control low-water mark */
669  u16 pause_time; /* Flow control pause timer */
670  bool send_xon; /* Flow control send XON */
671  bool strict_ieee; /* Strict IEEE mode */
672  e1000_fc_type type; /* Type of flow control */
673  e1000_fc_type original_type;
674 };
675 
676 struct e1000_hw {
677  void *back;
678  void *dev_spec;
679 
680  u8 __iomem *hw_addr;
681  u8 __iomem *flash_address;
682  unsigned long io_base;
683 
684  struct e1000_functions func;
685  struct e1000_mac_info mac;
686  struct e1000_fc_info fc;
687  struct e1000_phy_info phy;
688  struct e1000_nvm_info nvm;
689  struct e1000_bus_info bus;
690  struct e1000_host_mng_dhcp_cookie mng_cookie;
691 
692  u32 dev_spec_size;
693 
694  u16 device_id;
695  u16 subsystem_vendor_id;
696  u16 subsystem_device_id;
697  u16 vendor_id;
698 
699  u8 revision_id;
700 };
701 
702 /* These functions must be implemented by drivers */
703 void e1000_pci_clear_mwi(struct e1000_hw *hw);
704 void e1000_pci_set_mwi(struct e1000_hw *hw);
705 s32 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size);
706 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
707 void e1000_free_dev_spec_struct(struct e1000_hw *hw);
708 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
709 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
710 
711 #endif