Xenomai  3.0.8
e1000_osdep.h
1 /*******************************************************************************
2 
3  Intel PRO/1000 Linux driver
4  Copyright(c) 1999 - 2008 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Contact Information:
23  Linux NICS <linux.nics@intel.com>
24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 
30 /* glue for the OS-dependent part of e1000
31  * includes register access macros
32  */
33 
34 #ifndef _E1000_OSDEP_H_
35 #define _E1000_OSDEP_H_
36 
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/if_ether.h>
41 
42 #include "kcompat.h"
43 
44 #define usec_delay(x) udelay(x)
45 #ifndef msec_delay
46 #define msec_delay(x) do { if(in_interrupt()) { \
47  /* Don't sleep in interrupt context! */ \
48  BUG(); \
49  } else { \
50  msleep(x); \
51  } } while (0)
52 
53 /* Some workarounds require millisecond delays and are run during interrupt
54  * context. Most notably, when establishing link, the phy may need tweaking
55  * but cannot process phy register reads/writes faster than millisecond
56  * intervals...and we establish link due to a "link status change" interrupt.
57  */
58 #define msec_delay_irq(x) mdelay(x)
59 #endif
60 
61 #define PCI_COMMAND_REGISTER PCI_COMMAND
62 #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
63 #define ETH_ADDR_LEN ETH_ALEN
64 
65 #ifdef __BIG_ENDIAN
66 #define E1000_BIG_ENDIAN __BIG_ENDIAN
67 #endif
68 
69 
70 #define DEBUGOUT(S)
71 #define DEBUGOUT1(S, A...)
72 
73 #define DEBUGFUNC(F) DEBUGOUT(F "\n")
74 #define DEBUGOUT2 DEBUGOUT1
75 #define DEBUGOUT3 DEBUGOUT2
76 #define DEBUGOUT7 DEBUGOUT3
77 
78 #define E1000_REGISTER(a, reg) (((a)->mac.type >= e1000_82543) \
79  ? reg \
80  : e1000_translate_register_82542(reg))
81 
82 #define E1000_WRITE_REG(a, reg, value) ( \
83  writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg))))
84 
85 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_REGISTER(a, reg)))
86 
87 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
88  writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2))))
89 
90 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
91  readl((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))
92 
93 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
94 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
95 
96 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
97  writew((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1))))
98 
99 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
100  readw((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1)))
101 
102 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
103  writeb((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + (offset))))
104 
105 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
106  readb((a)->hw_addr + E1000_REGISTER(a, reg) + (offset)))
107 
108 #define E1000_WRITE_REG_IO(a, reg, offset) do { \
109  outl(reg, ((a)->io_base)); \
110  outl(offset, ((a)->io_base + 4)); } while(0)
111 
112 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
113 
114 #define E1000_WRITE_FLASH_REG(a, reg, value) ( \
115  writel((value), ((a)->flash_address + reg)))
116 
117 #define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
118  writew((value), ((a)->flash_address + reg)))
119 
120 #define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
121 
122 #define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
123 
124 #endif /* _E1000_OSDEP_H_ */