Xenomai  3.0.8
e1000_phy.h
1 /*******************************************************************************
2 
3  Intel PRO/1000 Linux driver
4  Copyright(c) 1999 - 2008 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Contact Information:
23  Linux NICS <linux.nics@intel.com>
24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #ifndef _E1000_PHY_H_
30 #define _E1000_PHY_H_
31 
32 typedef enum {
33  e1000_ms_hw_default = 0,
34  e1000_ms_force_master,
35  e1000_ms_force_slave,
36  e1000_ms_auto
37 } e1000_ms_type;
38 
39 typedef enum {
40  e1000_smart_speed_default = 0,
41  e1000_smart_speed_on,
42  e1000_smart_speed_off
43 } e1000_smart_speed;
44 
45 s32 e1000_check_downshift_generic(struct e1000_hw *hw);
46 s32 e1000_check_polarity_m88(struct e1000_hw *hw);
47 s32 e1000_check_polarity_igp(struct e1000_hw *hw);
48 s32 e1000_check_reset_block_generic(struct e1000_hw *hw);
49 s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
50 s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
51 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw);
52 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw);
53 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
54 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
55 s32 e1000_get_cable_length_m88(struct e1000_hw *hw);
56 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw);
57 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw);
58 s32 e1000_get_phy_id(struct e1000_hw *hw);
59 s32 e1000_get_phy_info_igp(struct e1000_hw *hw);
60 s32 e1000_get_phy_info_m88(struct e1000_hw *hw);
61 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw);
62 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
63 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw);
64 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
65 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
66 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
67 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
68 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
69 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
70 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw);
71 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw);
72 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
73 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
74 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
75 s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
76 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
77  u32 usec_interval, bool *success);
78 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
79 e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
80 void e1000_power_up_phy_copper(struct e1000_hw *hw);
81 void e1000_power_down_phy_copper(struct e1000_hw *hw);
82 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
83 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
84 
85 #define E1000_MAX_PHY_ADDR 4
86 
87 /* IGP01E1000 Specific Registers */
88 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
89 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
90 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
91 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
92 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
93 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */
94 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
95 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
96 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
97 #define IGP_PAGE_SHIFT 5
98 #define PHY_REG_MASK 0x1F
99 
100 
101 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
102 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
103 
104 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
105 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
106 
107 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
108 
109 /* Enable flexible speed on link-up */
110 #define IGP01E1000_GMII_FLEX_SPD 0x0010
111 #define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */
112 
113 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
114 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
115 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
116 
117 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
118 
119 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
120 #define IGP01E1000_PSSR_MDIX 0x0008
121 #define IGP01E1000_PSSR_SPEED_MASK 0xC000
122 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
123 
124 #define IGP02E1000_PHY_CHANNEL_NUM 4
125 #define IGP02E1000_PHY_AGC_A 0x11B1
126 #define IGP02E1000_PHY_AGC_B 0x12B1
127 #define IGP02E1000_PHY_AGC_C 0x14B1
128 #define IGP02E1000_PHY_AGC_D 0x18B1
129 
130 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
131 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
132 #define IGP02E1000_AGC_RANGE 15
133 
134 #define IGP03E1000_PHY_MISC_CTRL 0x1B
135 #define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */
136 
137 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF
138 
139 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
140 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
141 #define E1000_KMRNCTRLSTA_REN 0x00200000
142 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
143 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
144 
145 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
146 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
147 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
148 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
149 
150 /* IFE PHY Extended Status Control */
151 #define IFE_PESC_POLARITY_REVERSED 0x0100
152 
153 /* IFE PHY Special Control */
154 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
155 #define IFE_PSC_FORCE_POLARITY 0x0020
156 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
157 
158 /* IFE PHY Special Control and LED Control */
159 #define IFE_PSCL_PROBE_MODE 0x0020
160 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
161 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
162 
163 /* IFE PHY MDIX Control */
164 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
165 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
166 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
167 
168 #endif