Xenomai  3.0.8
igb.h
1 /* Intel(R) Gigabit Ethernet Linux driver
2  * Copyright(c) 2007-2014 Intel Corporation.
3  * RTnet port 2009 Vladimir Zapolskiy <vladimir.zapolskiy@siemens.com>
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, see <http://www.gnu.org/licenses/>.
16  *
17  * The full GNU General Public License is included in this distribution in
18  * the file called "COPYING".
19  *
20  * Contact Information:
21  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23  */
24 
25 /* Linux PRO/1000 Ethernet Driver main header file */
26 
27 #ifndef _IGB_H_
28 #define _IGB_H_
29 
30 #include "e1000_mac.h"
31 #include "e1000_82575.h"
32 
33 #include <linux/bitops.h>
34 #include <linux/if_vlan.h>
35 #include <linux/i2c.h>
36 #include <linux/i2c-algo-bit.h>
37 #include <linux/pci.h>
38 #include <linux/mdio.h>
39 
40 #include <rtdev.h>
41 
42 struct igb_adapter;
43 
44 #define E1000_PCS_CFG_IGN_SD 1
45 
46 /* Interrupt defines */
47 #define IGB_START_ITR 648 /* ~6000 ints/sec */
48 #define IGB_4K_ITR 980
49 #define IGB_20K_ITR 196
50 #define IGB_70K_ITR 56
51 
52 /* TX/RX descriptor defines */
53 #define IGB_DEFAULT_TXD 256
54 #define IGB_DEFAULT_TX_WORK 128
55 #define IGB_MIN_TXD 80
56 #define IGB_MAX_TXD 4096
57 
58 #define IGB_DEFAULT_RXD 256
59 #define IGB_MIN_RXD 80
60 #define IGB_MAX_RXD 4096
61 
62 #define IGB_DEFAULT_ITR 3 /* dynamic */
63 #define IGB_MAX_ITR_USECS 10000
64 #define IGB_MIN_ITR_USECS 10
65 #define NON_Q_VECTORS 1
66 #define MAX_Q_VECTORS 8
67 #define MAX_MSIX_ENTRIES 10
68 
69 /* Transmit and receive queues */
70 #define IGB_MAX_RX_QUEUES 8
71 #define IGB_MAX_RX_QUEUES_82575 4
72 #define IGB_MAX_RX_QUEUES_I211 2
73 #define IGB_MAX_TX_QUEUES 8
74 #define IGB_MAX_VF_MC_ENTRIES 30
75 #define IGB_MAX_VF_FUNCTIONS 8
76 #define IGB_MAX_VFTA_ENTRIES 128
77 #define IGB_82576_VF_DEV_ID 0x10CA
78 #define IGB_I350_VF_DEV_ID 0x1520
79 
80 /* NVM version defines */
81 #define IGB_MAJOR_MASK 0xF000
82 #define IGB_MINOR_MASK 0x0FF0
83 #define IGB_BUILD_MASK 0x000F
84 #define IGB_COMB_VER_MASK 0x00FF
85 #define IGB_MAJOR_SHIFT 12
86 #define IGB_MINOR_SHIFT 4
87 #define IGB_COMB_VER_SHFT 8
88 #define IGB_NVM_VER_INVALID 0xFFFF
89 #define IGB_ETRACK_SHIFT 16
90 #define NVM_ETRACK_WORD 0x0042
91 #define NVM_COMB_VER_OFF 0x0083
92 #define NVM_COMB_VER_PTR 0x003d
93 
94 struct vf_data_storage {
95  unsigned char vf_mac_addresses[ETH_ALEN];
96  u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
97  u16 num_vf_mc_hashes;
98  u16 vlans_enabled;
99  u32 flags;
100  unsigned long last_nack;
101  u16 pf_vlan; /* When set, guest VLAN config not allowed. */
102  u16 pf_qos;
103  u16 tx_rate;
104  bool spoofchk_enabled;
105 };
106 
107 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
108 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
109 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
110 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
111 
112 /* RX descriptor control thresholds.
113  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
114  * descriptors available in its onboard memory.
115  * Setting this to 0 disables RX descriptor prefetch.
116  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
117  * available in host memory.
118  * If PTHRESH is 0, this should also be 0.
119  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
120  * descriptors until either it has this many to write back, or the
121  * ITR timer expires.
122  */
123 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
124 #define IGB_RX_HTHRESH 8
125 #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
126 #define IGB_TX_HTHRESH 1
127 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
128  (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
129 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
130  (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
131 
132 /* this is the size past which hardware will drop packets when setting LPE=0 */
133 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
134 
135 /* Supported Rx Buffer Sizes */
136 #define IGB_RXBUFFER_256 256
137 #define IGB_RXBUFFER_2048 2048
138 #define IGB_RX_HDR_LEN IGB_RXBUFFER_256
139 #define IGB_RX_BUFSZ IGB_RXBUFFER_2048
140 
141 /* How many Rx Buffers do we bundle into one write to the hardware ? */
142 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
143 
144 #define AUTO_ALL_MODES 0
145 #define IGB_EEPROM_APME 0x0400
146 
147 #ifndef IGB_MASTER_SLAVE
148 /* Switch to override PHY master/slave setting */
149 #define IGB_MASTER_SLAVE e1000_ms_hw_default
150 #endif
151 
152 #define IGB_MNG_VLAN_NONE -1
153 
154 enum igb_tx_flags {
155  /* cmd_type flags */
156  IGB_TX_FLAGS_VLAN = 0x01,
157  IGB_TX_FLAGS_TSO = 0x02,
158  IGB_TX_FLAGS_TSTAMP = 0x04,
159 
160  /* olinfo flags */
161  IGB_TX_FLAGS_IPV4 = 0x10,
162  IGB_TX_FLAGS_CSUM = 0x20,
163 };
164 
165 /* VLAN info */
166 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
167 #define IGB_TX_FLAGS_VLAN_SHIFT 16
168 
169 /* The largest size we can write to the descriptor is 65535. In order to
170  * maintain a power of two alignment we have to limit ourselves to 32K.
171  */
172 #define IGB_MAX_TXD_PWR 15
173 #define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR)
174 
175 /* Tx Descriptors needed, worst case */
176 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
177 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
178 
179 /* EEPROM byte offsets */
180 #define IGB_SFF_8472_SWAP 0x5C
181 #define IGB_SFF_8472_COMP 0x5E
182 
183 /* Bitmasks */
184 #define IGB_SFF_ADDRESSING_MODE 0x4
185 #define IGB_SFF_8472_UNSUP 0x00
186 
187 /* wrapper around a pointer to a socket buffer,
188  * so a DMA handle can be stored along with the buffer
189  */
190 struct igb_tx_buffer {
191  union e1000_adv_tx_desc *next_to_watch;
192  unsigned long time_stamp;
193  struct rtskb *skb;
194  unsigned int bytecount;
195  u16 gso_segs;
196  __be16 protocol;
197 
198  u32 tx_flags;
199 };
200 
201 struct igb_rx_buffer {
202  dma_addr_t dma;
203  struct rtskb *skb;
204 };
205 
206 struct igb_tx_queue_stats {
207  u64 packets;
208  u64 bytes;
209  u64 restart_queue;
210  u64 restart_queue2;
211 };
212 
213 struct igb_rx_queue_stats {
214  u64 packets;
215  u64 bytes;
216  u64 drops;
217  u64 csum_err;
218  u64 alloc_failed;
219 };
220 
221 struct igb_ring_container {
222  struct igb_ring *ring; /* pointer to linked list of rings */
223  unsigned int total_bytes; /* total bytes processed this int */
224  unsigned int total_packets; /* total packets processed this int */
225  u16 work_limit; /* total work allowed per interrupt */
226  u8 count; /* total number of rings in vector */
227  u8 itr; /* current ITR setting for ring */
228 };
229 
230 struct igb_ring {
231  struct igb_q_vector *q_vector; /* backlink to q_vector */
232  struct rtnet_device *netdev; /* back pointer to net_device */
233  struct device *dev; /* device pointer for dma mapping */
234  union { /* array of buffer info structs */
235  struct igb_tx_buffer *tx_buffer_info;
236  struct igb_rx_buffer *rx_buffer_info;
237  };
238  void *desc; /* descriptor ring memory */
239  unsigned long flags; /* ring specific flags */
240  void __iomem *tail; /* pointer to ring tail register */
241  dma_addr_t dma; /* phys address of the ring */
242  unsigned int size; /* length of desc. ring in bytes */
243 
244  u16 count; /* number of desc. in the ring */
245  u8 queue_index; /* logical index of the ring*/
246  u8 reg_idx; /* physical index of the ring */
247 
248  /* everything past this point are written often */
249  u16 next_to_clean;
250  u16 next_to_use;
251  u16 next_to_alloc;
252 
253  union {
254  /* TX */
255  struct {
256  struct igb_tx_queue_stats tx_stats;
257  };
258  /* RX */
259  struct {
260  struct igb_rx_queue_stats rx_stats;
261  u16 rx_buffer_len;
262  };
263  };
264 } ____cacheline_internodealigned_in_smp;
265 
266 struct igb_q_vector {
267  struct igb_adapter *adapter; /* backlink */
268  int cpu; /* CPU for DCA */
269  u32 eims_value; /* EIMS mask value */
270 
271  u16 itr_val;
272  u8 set_itr;
273  void __iomem *itr_register;
274 
275  struct igb_ring_container rx, tx;
276 
277  struct rcu_head rcu; /* to avoid race with update stats on free */
278  char name[IFNAMSIZ + 9];
279 
280  /* for dynamic allocation of rings associated with this q_vector */
281  struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
282 };
283 
284 enum e1000_ring_flags_t {
285  IGB_RING_FLAG_RX_SCTP_CSUM,
286  IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
287  IGB_RING_FLAG_TX_CTX_IDX,
288  IGB_RING_FLAG_TX_DETECT_HANG
289 };
290 
291 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
292 
293 #define IGB_RX_DESC(R, i) \
294  (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
295 #define IGB_TX_DESC(R, i) \
296  (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
297 #define IGB_TX_CTXTDESC(R, i) \
298  (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
299 
300 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */
301 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
302  const u32 stat_err_bits)
303 {
304  return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
305 }
306 
307 /* igb_desc_unused - calculate if we have unused descriptors */
308 static inline int igb_desc_unused(struct igb_ring *ring)
309 {
310  if (ring->next_to_clean > ring->next_to_use)
311  return ring->next_to_clean - ring->next_to_use - 1;
312 
313  return ring->count + ring->next_to_clean - ring->next_to_use - 1;
314 }
315 
316 #ifdef CONFIG_IGB_HWMON
317 
318 #define IGB_HWMON_TYPE_LOC 0
319 #define IGB_HWMON_TYPE_TEMP 1
320 #define IGB_HWMON_TYPE_CAUTION 2
321 #define IGB_HWMON_TYPE_MAX 3
322 
323 struct hwmon_attr {
324  struct device_attribute dev_attr;
325  struct e1000_hw *hw;
326  struct e1000_thermal_diode_data *sensor;
327  char name[12];
328  };
329 
330 struct hwmon_buff {
331  struct attribute_group group;
332  const struct attribute_group *groups[2];
333  struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];
334  struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];
335  unsigned int n_hwmon;
336  };
337 #endif
338 
339 #define IGB_N_EXTTS 2
340 #define IGB_N_PEROUT 2
341 #define IGB_N_SDP 4
342 #define IGB_RETA_SIZE 128
343 
344 /* board specific private data structure */
345 struct igb_adapter {
346  unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
347 
348  struct rtnet_device *netdev;
349 
350  unsigned long state;
351  unsigned int flags;
352 
353  unsigned int num_q_vectors;
354  struct msix_entry msix_entries[MAX_MSIX_ENTRIES];
355  rtdm_irq_t msix_irq_handle[MAX_MSIX_ENTRIES];
356  rtdm_irq_t irq_handle;
357  rtdm_nrtsig_t watchdog_nrtsig;
358  spinlock_t stats64_lock;
359 
360  /* Interrupt Throttle Rate */
361  u32 rx_itr_setting;
362  u32 tx_itr_setting;
363  u16 tx_itr;
364  u16 rx_itr;
365 
366  /* TX */
367  u16 tx_work_limit;
368  u32 tx_timeout_count;
369  int num_tx_queues;
370  struct igb_ring *tx_ring[16];
371 
372  /* RX */
373  int num_rx_queues;
374  struct igb_ring *rx_ring[16];
375 
376  u32 max_frame_size;
377  u32 min_frame_size;
378 
379  struct timer_list watchdog_timer;
380  struct timer_list phy_info_timer;
381 
382  u16 mng_vlan_id;
383  u32 bd_number;
384  u32 wol;
385  u32 en_mng_pt;
386  u16 link_speed;
387  u16 link_duplex;
388 
389  struct work_struct reset_task;
390  struct work_struct watchdog_task;
391  bool fc_autoneg;
392  u8 tx_timeout_factor;
393  struct timer_list blink_timer;
394  unsigned long led_status;
395 
396  /* OS defined structs */
397  struct pci_dev *pdev;
398 
399  struct net_device_stats net_stats;
400 
401  /* structs defined in e1000_hw.h */
402  struct e1000_hw hw;
403  struct e1000_hw_stats stats;
404  struct e1000_phy_info phy_info;
405 
406  u32 test_icr;
407  struct igb_ring test_tx_ring;
408  struct igb_ring test_rx_ring;
409 
410  struct igb_q_vector *q_vector[MAX_Q_VECTORS];
411  u32 eims_enable_mask;
412  u32 eims_other;
413 
414  /* to not mess up cache alignment, always add to the bottom */
415  u16 tx_ring_count;
416  u16 rx_ring_count;
417  int vf_rate_link_speed;
418  u32 rss_queues;
419  u32 wvbr;
420  u32 *shadow_vfta;
421 
422  unsigned long last_rx_timestamp;
423 
424  char fw_version[32];
425 #ifdef CONFIG_IGB_HWMON
426  struct hwmon_buff *igb_hwmon_buff;
427  bool ets;
428 #endif
429  struct i2c_algo_bit_data i2c_algo;
430  struct i2c_adapter i2c_adap;
431  struct i2c_client *i2c_client;
432  u32 rss_indir_tbl_init;
433  u8 rss_indir_tbl[IGB_RETA_SIZE];
434 
435  unsigned long link_check_timeout;
436  int copper_tries;
437  struct e1000_info ei;
438  u16 eee_advert;
439 };
440 
441 #define IGB_FLAG_HAS_MSI (1 << 0)
442 #define IGB_FLAG_DCA_ENABLED (1 << 1)
443 #define IGB_FLAG_QUAD_PORT_A (1 << 2)
444 #define IGB_FLAG_QUEUE_PAIRS (1 << 3)
445 #define IGB_FLAG_DMAC (1 << 4)
446 #define IGB_FLAG_PTP (1 << 5)
447 #define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6)
448 #define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7)
449 #define IGB_FLAG_WOL_SUPPORTED (1 << 8)
450 #define IGB_FLAG_NEED_LINK_UPDATE (1 << 9)
451 #define IGB_FLAG_MEDIA_RESET (1 << 10)
452 #define IGB_FLAG_MAS_CAPABLE (1 << 11)
453 #define IGB_FLAG_MAS_ENABLE (1 << 12)
454 #define IGB_FLAG_HAS_MSIX (1 << 13)
455 #define IGB_FLAG_EEE (1 << 14)
456 
457 /* Media Auto Sense */
458 #define IGB_MAS_ENABLE_0 0X0001
459 #define IGB_MAS_ENABLE_1 0X0002
460 #define IGB_MAS_ENABLE_2 0X0004
461 #define IGB_MAS_ENABLE_3 0X0008
462 
463 /* DMA Coalescing defines */
464 #define IGB_MIN_TXPBSIZE 20408
465 #define IGB_TX_BUF_4096 4096
466 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
467 
468 #define IGB_82576_TSYNC_SHIFT 19
469 #define IGB_TS_HDR_LEN 16
470 enum e1000_state_t {
471  __IGB_TESTING,
472  __IGB_RESETTING,
473  __IGB_DOWN,
474  __IGB_PTP_TX_IN_PROGRESS,
475 };
476 
477 enum igb_boards {
478  board_82575,
479 };
480 
481 extern char igb_driver_name[];
482 extern char igb_driver_version[];
483 
484 int igb_up(struct igb_adapter *);
485 void igb_down(struct igb_adapter *);
486 void igb_reinit_locked(struct igb_adapter *);
487 void igb_reset(struct igb_adapter *);
488 int igb_reinit_queues(struct igb_adapter *);
489 void igb_write_rss_indir_tbl(struct igb_adapter *);
490 int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
491 int igb_setup_tx_resources(struct igb_ring *);
492 int igb_setup_rx_resources(struct igb_ring *);
493 void igb_free_tx_resources(struct igb_ring *);
494 void igb_free_rx_resources(struct igb_ring *);
495 void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
496 void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
497 void igb_setup_tctl(struct igb_adapter *);
498 void igb_setup_rctl(struct igb_adapter *);
499 netdev_tx_t igb_xmit_frame_ring(struct rtskb *, struct igb_ring *);
500 void igb_unmap_and_free_tx_resource(struct igb_ring *, struct igb_tx_buffer *);
501 void igb_alloc_rx_buffers(struct igb_ring *, u16);
502 void igb_update_stats(struct igb_adapter *);
503 bool igb_has_link(struct igb_adapter *adapter);
504 void igb_set_ethtool_ops(struct rtnet_device *);
505 void igb_power_up_link(struct igb_adapter *);
506 void igb_set_fw_version(struct igb_adapter *);
507 void igb_ptp_init(struct igb_adapter *adapter);
508 void igb_ptp_stop(struct igb_adapter *adapter);
509 void igb_ptp_reset(struct igb_adapter *adapter);
510 void igb_ptp_rx_hang(struct igb_adapter *adapter);
511 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct rtskb *skb);
512 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, unsigned char *va,
513  struct rtskb *skb);
514 int igb_ptp_set_ts_config(struct rtnet_device *netdev, struct ifreq *ifr);
515 int igb_ptp_get_ts_config(struct rtnet_device *netdev, struct ifreq *ifr);
516 #ifdef CONFIG_IGB_HWMON
517 void igb_sysfs_exit(struct igb_adapter *adapter);
518 int igb_sysfs_init(struct igb_adapter *adapter);
519 #endif
520 static inline s32 igb_reset_phy(struct e1000_hw *hw)
521 {
522  if (hw->phy.ops.reset)
523  return hw->phy.ops.reset(hw);
524 
525  return 0;
526 }
527 
528 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
529 {
530  if (hw->phy.ops.read_reg)
531  return hw->phy.ops.read_reg(hw, offset, data);
532 
533  return 0;
534 }
535 
536 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
537 {
538  if (hw->phy.ops.write_reg)
539  return hw->phy.ops.write_reg(hw, offset, data);
540 
541  return 0;
542 }
543 
544 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
545 {
546  if (hw->phy.ops.get_phy_info)
547  return hw->phy.ops.get_phy_info(hw);
548 
549  return 0;
550 }
551 
552 static inline struct rtnet_device *txring_txq(const struct igb_ring *tx_ring)
553 {
554  return tx_ring->netdev;
555 }
556 
557 #endif /* _IGB_H_ */