Xenomai  3.0.8
mite.h
1 /*
2  * Hardware driver for NI Mite PCI interface chip
3  * @note Copyright (C) 1999 David A. Schleef <ds@schleef.org>
4  *
5  * This library is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU Lesser General Public
7  * License as published by the Free Software Foundation; either
8  * version 2 of the License, or (at your option) any later version.
9  *
10  * This library is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13  * Lesser General Public License for more details.
14 
15  * You should have received a copy of the GNU Lesser General Public
16  * License along with this library; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
18  */
19 #ifndef __ANALOGY_NI_MITE_H__
20 #define __ANALOGY_NI_MITE_H__
21 
22 #include <linux/pci.h>
23 #include <linux/slab.h>
24 #include <rtdm/analogy/device.h>
25 
26 #define PCI_VENDOR_ID_NATINST 0x1093
27 #define PCI_MITE_SIZE 4096
28 #define PCI_DAQ_SIZE 4096
29 #define PCI_DAQ_SIZE_660X 8192
30 #define PCIMIO_COMPAT
31 #define MAX_MITE_DMA_CHANNELS 8
32 
33 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
34 
35 struct mite_dma_descriptor {
36  u32 count;
37  u32 addr;
38  u32 next;
39  u32 dar;
40 };
41 
42 struct mite_dma_descriptor_ring {
43  struct pci_dev *pcidev;
44  u32 n_links;
45  struct mite_dma_descriptor *descriptors;
46  dma_addr_t descriptors_dma_addr;
47 };
48 
49 struct mite_channel {
50  struct mite_struct *mite;
51  u32 channel;
52  u32 dir;
53  u32 done;
54  struct mite_dma_descriptor_ring *ring;
55 };
56 
57 struct mite_struct {
58  struct list_head list;
59  rtdm_lock_t lock;
60  u32 used;
61  u32 num_channels;
62 
63  struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
64  u32 channel_allocated[MAX_MITE_DMA_CHANNELS];
65 
66  struct pci_dev *pcidev;
67  resource_size_t mite_phys_addr;
68  void *mite_io_addr;
69  resource_size_t daq_phys_addr;
70  void *daq_io_addr;
71 };
72 
73 static inline
74 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite)
75 {
76  struct mite_dma_descriptor_ring *ring =
77  kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_DMA);
78 
79  if (ring == NULL)
80  return ring;
81 
82  memset(ring, 0, sizeof(struct mite_dma_descriptor_ring));
83 
84  ring->pcidev = mite->pcidev;
85  if (ring->pcidev == NULL) {
86  kfree(ring);
87  return NULL;
88  }
89 
90  return ring;
91 };
92 
93 static inline void mite_free_ring(struct mite_dma_descriptor_ring *ring)
94 {
95  if (ring) {
96  if (ring->descriptors) {
97  pci_free_consistent(
98  ring->pcidev,
99  ring->n_links *
100  sizeof(struct mite_dma_descriptor),
101  ring->descriptors, ring->descriptors_dma_addr);
102  }
103  kfree(ring);
104  }
105 };
106 
107 static inline unsigned int mite_irq(struct mite_struct *mite)
108 {
109  return mite->pcidev->irq;
110 };
111 static inline unsigned int mite_device_id(struct mite_struct *mite)
112 {
113  return mite->pcidev->device;
114 };
115 
116 int a4l_mite_setup(struct mite_struct *mite, int use_iodwbsr_1);
117 void a4l_mite_unsetup(struct mite_struct *mite);
118 void a4l_mite_list_devices(void);
119 struct mite_struct * a4l_mite_find_device(int bus,
120  int slot, unsigned short device_id);
121 struct mite_channel *
122 a4l_mite_request_channel_in_range(struct mite_struct *mite,
123  struct mite_dma_descriptor_ring *ring,
124  unsigned min_channel, unsigned max_channel);
125 static inline struct mite_channel *mite_request_channel(struct mite_struct
126  *mite, struct mite_dma_descriptor_ring *ring)
127 {
128  return a4l_mite_request_channel_in_range(mite, ring, 0,
129  mite->num_channels - 1);
130 }
131 void a4l_mite_release_channel(struct mite_channel *mite_chan);
132 
133 void a4l_mite_dma_arm(struct mite_channel *mite_chan);
134 void a4l_mite_dma_disarm(struct mite_channel *mite_chan);
135 int a4l_mite_sync_input_dma(struct mite_channel *mite_chan, struct a4l_subdevice *subd);
136 int a4l_mite_sync_output_dma(struct mite_channel *mite_chan, struct a4l_subdevice *subd);
137 u32 a4l_mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
138 u32 a4l_mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
139 u32 a4l_mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
140 u32 a4l_mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
141 u32 a4l_mite_bytes_in_transit(struct mite_channel *mite_chan);
142 u32 a4l_mite_get_status(struct mite_channel *mite_chan);
143 int a4l_mite_done(struct mite_channel *mite_chan);
144 void a4l_mite_prep_dma(struct mite_channel *mite_chan,
145  unsigned int num_device_bits, unsigned int num_memory_bits);
146 int a4l_mite_buf_change(struct mite_dma_descriptor_ring *ring, struct a4l_subdevice *subd);
147 
148 #ifdef CONFIG_DEBUG_MITE
149 void mite_print_chsr(unsigned int chsr);
150 void a4l_mite_dump_regs(struct mite_channel *mite_chan);
151 #endif
152 
153 static inline int CHAN_OFFSET(int channel)
154 {
155  return 0x500 + 0x100 * channel;
156 };
157 
158 enum mite_registers {
159  /* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
160  written and read back. The bits 0x1f always read as 1.
161  The rest always read as zero. */
162  MITE_UNKNOWN_DMA_BURST_REG = 0x28,
163  MITE_IODWBSR = 0xc0, //IO Device Window Base Size Register
164  MITE_IODWBSR_1 = 0xc4, // IO Device Window Base Size Register 1
165  MITE_IODWCR_1 = 0xf4,
166  MITE_PCI_CONFIG_OFFSET = 0x300,
167  MITE_CSIGR = 0x460 //chip signature
168 };
169 static inline int MITE_CHOR(int channel) // channel operation
170 {
171  return CHAN_OFFSET(channel) + 0x0;
172 };
173 static inline int MITE_CHCR(int channel) // channel control
174 {
175  return CHAN_OFFSET(channel) + 0x4;
176 };
177 static inline int MITE_TCR(int channel) // transfer count
178 {
179  return CHAN_OFFSET(channel) + 0x8;
180 };
181 static inline int MITE_MCR(int channel) // memory configuration
182 {
183  return CHAN_OFFSET(channel) + 0xc;
184 };
185 static inline int MITE_MAR(int channel) // memory address
186 {
187  return CHAN_OFFSET(channel) + 0x10;
188 };
189 static inline int MITE_DCR(int channel) // device configuration
190 {
191  return CHAN_OFFSET(channel) + 0x14;
192 };
193 static inline int MITE_DAR(int channel) // device address
194 {
195  return CHAN_OFFSET(channel) + 0x18;
196 };
197 static inline int MITE_LKCR(int channel) // link configuration
198 {
199  return CHAN_OFFSET(channel) + 0x1c;
200 };
201 static inline int MITE_LKAR(int channel) // link address
202 {
203  return CHAN_OFFSET(channel) + 0x20;
204 };
205 static inline int MITE_LLKAR(int channel) // see mite section of tnt5002 manual
206 {
207  return CHAN_OFFSET(channel) + 0x24;
208 };
209 static inline int MITE_BAR(int channel) // base address
210 {
211  return CHAN_OFFSET(channel) + 0x28;
212 };
213 static inline int MITE_BCR(int channel) // base count
214 {
215  return CHAN_OFFSET(channel) + 0x2c;
216 };
217 static inline int MITE_SAR(int channel) // ? address
218 {
219  return CHAN_OFFSET(channel) + 0x30;
220 };
221 static inline int MITE_WSCR(int channel) // ?
222 {
223  return CHAN_OFFSET(channel) + 0x34;
224 };
225 static inline int MITE_WSER(int channel) // ?
226 {
227  return CHAN_OFFSET(channel) + 0x38;
228 };
229 static inline int MITE_CHSR(int channel) // channel status
230 {
231  return CHAN_OFFSET(channel) + 0x3c;
232 };
233 static inline int MITE_FCR(int channel) // fifo count
234 {
235  return CHAN_OFFSET(channel) + 0x40;
236 };
237 
238 enum MITE_IODWBSR_bits {
239  WENAB = 0x80, // window enable
240 };
241 
242 static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
243 {
244  unsigned order = 0;
245  while (size >>= 1)
246  ++order;
247  BUG_ON(order < 1);
248  return (order - 1) & 0x1f;
249 }
250 
251 enum MITE_UNKNOWN_DMA_BURST_bits {
252  UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
253 };
254 
255 static inline int mite_csigr_version(u32 csigr_bits)
256 {
257  return csigr_bits & 0xf;
258 };
259 static inline int mite_csigr_type(u32 csigr_bits)
260 { // original mite = 0, minimite = 1
261  return (csigr_bits >> 4) & 0xf;
262 };
263 static inline int mite_csigr_mmode(u32 csigr_bits)
264 { // mite mode, minimite = 1
265  return (csigr_bits >> 8) & 0x3;
266 };
267 static inline int mite_csigr_imode(u32 csigr_bits)
268 { // cpu port interface mode, pci = 0x3
269  return (csigr_bits >> 12) & 0x3;
270 };
271 static inline int mite_csigr_dmac(u32 csigr_bits)
272 { // number of dma channels
273  return (csigr_bits >> 16) & 0xf;
274 };
275 static inline int mite_csigr_wpdep(u32 csigr_bits)
276 { // write post fifo depth
277  unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
278  if (wpdep_bits == 0)
279  return 0;
280  else
281  return 1 << (wpdep_bits - 1);
282 };
283 static inline int mite_csigr_wins(u32 csigr_bits)
284 {
285  return (csigr_bits >> 24) & 0x1f;
286 };
287 static inline int mite_csigr_iowins(u32 csigr_bits)
288 { // number of io windows
289  return (csigr_bits >> 29) & 0x7;
290 };
291 
292 enum MITE_MCR_bits {
293  MCRPON = 0,
294 };
295 
296 enum MITE_DCR_bits {
297  DCR_NORMAL = (1 << 29),
298  DCRPON = 0,
299 };
300 
301 enum MITE_CHOR_bits {
302  CHOR_DMARESET = (1 << 31),
303  CHOR_SET_SEND_TC = (1 << 11),
304  CHOR_CLR_SEND_TC = (1 << 10),
305  CHOR_SET_LPAUSE = (1 << 9),
306  CHOR_CLR_LPAUSE = (1 << 8),
307  CHOR_CLRDONE = (1 << 7),
308  CHOR_CLRRB = (1 << 6),
309  CHOR_CLRLC = (1 << 5),
310  CHOR_FRESET = (1 << 4),
311  CHOR_ABORT = (1 << 3), /* stop without emptying fifo */
312  CHOR_STOP = (1 << 2), /* stop after emptying fifo */
313  CHOR_CONT = (1 << 1),
314  CHOR_START = (1 << 0),
315  CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
316 };
317 
318 enum MITE_CHCR_bits {
319  CHCR_SET_DMA_IE = (1 << 31),
320  CHCR_CLR_DMA_IE = (1 << 30),
321  CHCR_SET_LINKP_IE = (1 << 29),
322  CHCR_CLR_LINKP_IE = (1 << 28),
323  CHCR_SET_SAR_IE = (1 << 27),
324  CHCR_CLR_SAR_IE = (1 << 26),
325  CHCR_SET_DONE_IE = (1 << 25),
326  CHCR_CLR_DONE_IE = (1 << 24),
327  CHCR_SET_MRDY_IE = (1 << 23),
328  CHCR_CLR_MRDY_IE = (1 << 22),
329  CHCR_SET_DRDY_IE = (1 << 21),
330  CHCR_CLR_DRDY_IE = (1 << 20),
331  CHCR_SET_LC_IE = (1 << 19),
332  CHCR_CLR_LC_IE = (1 << 18),
333  CHCR_SET_CONT_RB_IE = (1 << 17),
334  CHCR_CLR_CONT_RB_IE = (1 << 16),
335  CHCR_FIFODIS = (1 << 15),
336  CHCR_FIFO_ON = 0,
337  CHCR_BURSTEN = (1 << 14),
338  CHCR_NO_BURSTEN = 0,
339  CHCR_BYTE_SWAP_DEVICE = (1 << 6),
340  CHCR_BYTE_SWAP_MEMORY = (1 << 4),
341  CHCR_DIR = (1 << 3),
342  CHCR_DEV_TO_MEM = CHCR_DIR,
343  CHCR_MEM_TO_DEV = 0,
344  CHCR_NORMAL = (0 << 0),
345  CHCR_CONTINUE = (1 << 0),
346  CHCR_RINGBUFF = (2 << 0),
347  CHCR_LINKSHORT = (4 << 0),
348  CHCR_LINKLONG = (5 << 0),
349  CHCRPON =
350  (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
351  CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
352  CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
353 };
354 
355 enum ConfigRegister_bits {
356  CR_REQS_MASK = 0x7 << 16,
357  CR_ASEQDONT = 0x0 << 10,
358  CR_ASEQUP = 0x1 << 10,
359  CR_ASEQDOWN = 0x2 << 10,
360  CR_ASEQ_MASK = 0x3 << 10,
361  CR_PSIZE8 = (1 << 8),
362  CR_PSIZE16 = (2 << 8),
363  CR_PSIZE32 = (3 << 8),
364  CR_PORTCPU = (0 << 6),
365  CR_PORTIO = (1 << 6),
366  CR_PORTVXI = (2 << 6),
367  CR_PORTMXI = (3 << 6),
368  CR_AMDEVICE = (1 << 0),
369 };
370 static inline int CR_REQS(int source)
371 {
372  return (source & 0x7) << 16;
373 };
374 static inline int CR_REQSDRQ(unsigned drq_line)
375 {
376  /* This also works on m-series when
377  using channels (drq_line) 4 or 5. */
378  return CR_REQS((drq_line & 0x3) | 0x4);
379 }
380 static inline int CR_RL(unsigned int retry_limit)
381 {
382  int value = 0;
383 
384  while (retry_limit) {
385  retry_limit >>= 1;
386  value++;
387  }
388  if (value > 0x7)
389  __a4l_err("bug! retry_limit too large\n");
390 
391  return (value & 0x7) << 21;
392 }
393 
394 enum CHSR_bits {
395  CHSR_INT = (1 << 31),
396  CHSR_LPAUSES = (1 << 29),
397  CHSR_SARS = (1 << 27),
398  CHSR_DONE = (1 << 25),
399  CHSR_MRDY = (1 << 23),
400  CHSR_DRDY = (1 << 21),
401  CHSR_LINKC = (1 << 19),
402  CHSR_CONTS_RB = (1 << 17),
403  CHSR_ERROR = (1 << 15),
404  CHSR_SABORT = (1 << 14),
405  CHSR_HABORT = (1 << 13),
406  CHSR_STOPS = (1 << 12),
407  CHSR_OPERR_mask = (3 << 10),
408  CHSR_OPERR_NOERROR = (0 << 10),
409  CHSR_OPERR_FIFOERROR = (1 << 10),
410  CHSR_OPERR_LINKERROR = (1 << 10), /* ??? */
411  CHSR_XFERR = (1 << 9),
412  CHSR_END = (1 << 8),
413  CHSR_DRQ1 = (1 << 7),
414  CHSR_DRQ0 = (1 << 6),
415  CHSR_LxERR_mask = (3 << 4),
416  CHSR_LBERR = (1 << 4),
417  CHSR_LRERR = (2 << 4),
418  CHSR_LOERR = (3 << 4),
419  CHSR_MxERR_mask = (3 << 2),
420  CHSR_MBERR = (1 << 2),
421  CHSR_MRERR = (2 << 2),
422  CHSR_MOERR = (3 << 2),
423  CHSR_DxERR_mask = (3 << 0),
424  CHSR_DBERR = (1 << 0),
425  CHSR_DRERR = (2 << 0),
426  CHSR_DOERR = (3 << 0),
427 };
428 
429 static inline void mite_dma_reset(struct mite_channel *mite_chan)
430 {
431  writel(CHOR_DMARESET | CHOR_FRESET,
432  mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
433 };
434 
435 #endif /* !__ANALOGY_NI_MITE_H__ */
ipipe_spinlock_t rtdm_lock_t
Lock variable.
Definition: driver.h:551
Structure describing the subdevice.
Definition: subdevice.h:40