Xenomai  3.0.8
ni_stc.h
1 /*
2  * Register descriptions for NI DAQ-STC chip
3  *
4  * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
5  *
6  * This code is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published
8  * by the Free Software Foundation; either version 2 of the License,
9  * or (at your option) any later version.
10  *
11  * This code is distributed in the hope that it will be useful, but
12  * WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14  * General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this code; if not, write to the Free Software Foundation,
18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  *
20  * References:
21  * 340934b.pdf DAQ-STC reference manual
22  *
23  */
24 #ifndef __ANALOGY_NI_STC_H__
25 #define __ANALOGY_NI_STC_H__
26 
27 #include "ni_tio.h"
28 
29 #define _bit15 0x8000
30 #define _bit14 0x4000
31 #define _bit13 0x2000
32 #define _bit12 0x1000
33 #define _bit11 0x0800
34 #define _bit10 0x0400
35 #define _bit9 0x0200
36 #define _bit8 0x0100
37 #define _bit7 0x0080
38 #define _bit6 0x0040
39 #define _bit5 0x0020
40 #define _bit4 0x0010
41 #define _bit3 0x0008
42 #define _bit2 0x0004
43 #define _bit1 0x0002
44 #define _bit0 0x0001
45 
46 #define NUM_PFI_OUTPUT_SELECT_REGS 6
47 
48 /* Registers in the National Instruments DAQ-STC chip */
49 
50 #define Interrupt_A_Ack_Register 2
51 #define G0_Gate_Interrupt_Ack _bit15
52 #define G0_TC_Interrupt_Ack _bit14
53 #define AI_Error_Interrupt_Ack _bit13
54 #define AI_STOP_Interrupt_Ack _bit12
55 #define AI_START_Interrupt_Ack _bit11
56 #define AI_START2_Interrupt_Ack _bit10
57 #define AI_START1_Interrupt_Ack _bit9
58 #define AI_SC_TC_Interrupt_Ack _bit8
59 #define AI_SC_TC_Error_Confirm _bit7
60 #define G0_TC_Error_Confirm _bit6
61 #define G0_Gate_Error_Confirm _bit5
62 
63 #define AI_Status_1_Register 2
64 #define Interrupt_A_St _bit15
65 #define AI_FIFO_Full_St _bit14
66 #define AI_FIFO_Half_Full_St _bit13
67 #define AI_FIFO_Empty_St _bit12
68 #define AI_Overrun_St _bit11
69 #define AI_Overflow_St _bit10
70 #define AI_SC_TC_Error_St _bit9
71 #define AI_START2_St _bit8
72 #define AI_START1_St _bit7
73 #define AI_SC_TC_St _bit6
74 #define AI_START_St _bit5
75 #define AI_STOP_St _bit4
76 #define G0_TC_St _bit3
77 #define G0_Gate_Interrupt_St _bit2
78 #define AI_FIFO_Request_St _bit1
79 #define Pass_Thru_0_Interrupt_St _bit0
80 
81 #define AI_Status_2_Register 5
82 
83 #define Interrupt_B_Ack_Register 3
84 #define G1_Gate_Error_Confirm _bit1
85 #define G1_TC_Error_Confirm _bit2
86 #define AO_BC_TC_Trigger_Error_Confirm _bit3
87 #define AO_BC_TC_Error_Confirm _bit4
88 #define AO_UI2_TC_Error_Confrim _bit5
89 #define AO_UI2_TC_Interrupt_Ack _bit6
90 #define AO_UC_TC_Interrupt_Ack _bit7
91 #define AO_BC_TC_Interrupt_Ack _bit8
92 #define AO_START1_Interrupt_Ack _bit9
93 #define AO_UPDATE_Interrupt_Ack _bit10
94 #define AO_START_Interrupt_Ack _bit11
95 #define AO_STOP_Interrupt_Ack _bit12
96 #define AO_Error_Interrupt_Ack _bit13
97 #define G1_TC_Interrupt_Ack _bit14
98 #define G1_Gate_Interrupt_Ack _bit15
99 
100 #define AO_Status_1_Register 3
101 #define Interrupt_B_St _bit15
102 #define AO_FIFO_Full_St _bit14
103 #define AO_FIFO_Half_Full_St _bit13
104 #define AO_FIFO_Empty_St _bit12
105 #define AO_BC_TC_Error_St _bit11
106 #define AO_START_St _bit10
107 #define AO_Overrun_St _bit9
108 #define AO_START1_St _bit8
109 #define AO_BC_TC_St _bit7
110 #define AO_UC_TC_St _bit6
111 #define AO_UPDATE_St _bit5
112 #define AO_UI2_TC_St _bit4
113 #define G1_TC_St _bit3
114 #define G1_Gate_Interrupt_St _bit2
115 #define AO_FIFO_Request_St _bit1
116 #define Pass_Thru_1_Interrupt_St _bit0
117 
118 
119 #define AI_Command_2_Register 4
120 #define AI_End_On_SC_TC _bit15
121 #define AI_End_On_End_Of_Scan _bit14
122 #define AI_START1_Disable _bit11
123 #define AI_SC_Save_Trace _bit10
124 #define AI_SI_Switch_Load_On_SC_TC _bit9
125 #define AI_SI_Switch_Load_On_STOP _bit8
126 #define AI_SI_Switch_Load_On_TC _bit7
127 #define AI_SC_Switch_Load_On_TC _bit4
128 #define AI_STOP_Pulse _bit3
129 #define AI_START_Pulse _bit2
130 #define AI_START2_Pulse _bit1
131 #define AI_START1_Pulse _bit0
132 
133 #define AO_Command_2_Register 5
134 #define AO_End_On_BC_TC(x) (((x) & 0x3) << 14)
135 #define AO_Start_Stop_Gate_Enable _bit13
136 #define AO_UC_Save_Trace _bit12
137 #define AO_BC_Gate_Enable _bit11
138 #define AO_BC_Save_Trace _bit10
139 #define AO_UI_Switch_Load_On_BC_TC _bit9
140 #define AO_UI_Switch_Load_On_Stop _bit8
141 #define AO_UI_Switch_Load_On_TC _bit7
142 #define AO_UC_Switch_Load_On_BC_TC _bit6
143 #define AO_UC_Switch_Load_On_TC _bit5
144 #define AO_BC_Switch_Load_On_TC _bit4
145 #define AO_Mute_B _bit3
146 #define AO_Mute_A _bit2
147 #define AO_UPDATE2_Pulse _bit1
148 #define AO_START1_Pulse _bit0
149 
150 #define AO_Status_2_Register 6
151 
152 #define DIO_Parallel_Input_Register 7
153 
154 #define AI_Command_1_Register 8
155 #define AI_Analog_Trigger_Reset _bit14
156 #define AI_Disarm _bit13
157 #define AI_SI2_Arm _bit12
158 #define AI_SI2_Load _bit11
159 #define AI_SI_Arm _bit10
160 #define AI_SI_Load _bit9
161 #define AI_DIV_Arm _bit8
162 #define AI_DIV_Load _bit7
163 #define AI_SC_Arm _bit6
164 #define AI_SC_Load _bit5
165 #define AI_SCAN_IN_PROG_Pulse _bit4
166 #define AI_EXTMUX_CLK_Pulse _bit3
167 #define AI_LOCALMUX_CLK_Pulse _bit2
168 #define AI_SC_TC_Pulse _bit1
169 #define AI_CONVERT_Pulse _bit0
170 
171 #define AO_Command_1_Register 9
172 #define AO_Analog_Trigger_Reset _bit15
173 #define AO_START_Pulse _bit14
174 #define AO_Disarm _bit13
175 #define AO_UI2_Arm_Disarm _bit12
176 #define AO_UI2_Load _bit11
177 #define AO_UI_Arm _bit10
178 #define AO_UI_Load _bit9
179 #define AO_UC_Arm _bit8
180 #define AO_UC_Load _bit7
181 #define AO_BC_Arm _bit6
182 #define AO_BC_Load _bit5
183 #define AO_DAC1_Update_Mode _bit4
184 #define AO_LDAC1_Source_Select _bit3
185 #define AO_DAC0_Update_Mode _bit2
186 #define AO_LDAC0_Source_Select _bit1
187 #define AO_UPDATE_Pulse _bit0
188 
189 
190 #define DIO_Output_Register 10
191 #define DIO_Parallel_Data_Out(a) ((a)&0xff)
192 #define DIO_Parallel_Data_Mask 0xff
193 #define DIO_SDOUT _bit0
194 #define DIO_SDIN _bit4
195 #define DIO_Serial_Data_Out(a) (((a)&0xff)<<8)
196 #define DIO_Serial_Data_Mask 0xff00
197 
198 #define DIO_Control_Register 11
199 #define DIO_Software_Serial_Control _bit11
200 #define DIO_HW_Serial_Timebase _bit10
201 #define DIO_HW_Serial_Enable _bit9
202 #define DIO_HW_Serial_Start _bit8
203 #define DIO_Pins_Dir(a) ((a)&0xff)
204 #define DIO_Pins_Dir_Mask 0xff
205 
206 #define AI_Mode_1_Register 12
207 #define AI_CONVERT_Source_Select(a) (((a) & 0x1f) << 11)
208 #define AI_SI_Source_select(a) (((a) & 0x1f) << 6)
209 #define AI_CONVERT_Source_Polarity _bit5
210 #define AI_SI_Source_Polarity _bit4
211 #define AI_Start_Stop _bit3
212 #define AI_Mode_1_Reserved _bit2
213 #define AI_Continuous _bit1
214 #define AI_Trigger_Once _bit0
215 
216 #define AI_Mode_2_Register 13
217 #define AI_SC_Gate_Enable _bit15
218 #define AI_Start_Stop_Gate_Enable _bit14
219 #define AI_Pre_Trigger _bit13
220 #define AI_External_MUX_Present _bit12
221 #define AI_SI2_Initial_Load_Source _bit9
222 #define AI_SI2_Reload_Mode _bit8
223 #define AI_SI_Initial_Load_Source _bit7
224 #define AI_SI_Reload_Mode(a) (((a) & 0x7)<<4)
225 #define AI_SI_Write_Switch _bit3
226 #define AI_SC_Initial_Load_Source _bit2
227 #define AI_SC_Reload_Mode _bit1
228 #define AI_SC_Write_Switch _bit0
229 
230 #define AI_SI_Load_A_Registers 14
231 #define AI_SI_Load_B_Registers 16
232 #define AI_SC_Load_A_Registers 18
233 #define AI_SC_Load_B_Registers 20
234 #define AI_SI_Save_Registers 64
235 #define AI_SC_Save_Registers 66
236 
237 #define AI_SI2_Load_A_Register 23
238 #define AI_SI2_Load_B_Register 25
239 
240 #define Joint_Status_1_Register 27
241 #define DIO_Serial_IO_In_Progress_St _bit12
242 
243 #define DIO_Serial_Input_Register 28
244 #define Joint_Status_2_Register 29
245 #define AO_TMRDACWRs_In_Progress_St _bit5
246 
247 #define AO_Mode_1_Register 38
248 #define AO_UPDATE_Source_Select(x) (((x)&0x1f)<<11)
249 #define AO_UI_Source_Select(x) (((x)&0x1f)<<6)
250 #define AO_Multiple_Channels _bit5
251 #define AO_UPDATE_Source_Polarity _bit4
252 #define AO_UI_Source_Polarity _bit3
253 #define AO_UC_Switch_Load_Every_TC _bit2
254 #define AO_Continuous _bit1
255 #define AO_Trigger_Once _bit0
256 
257 #define AO_Mode_2_Register 39
258 #define AO_FIFO_Mode_Mask ( 0x3 << 14 )
259 #define AO_FIFO_Mode_HF_to_F (3<<14)
260 #define AO_FIFO_Mode_F (2<<14)
261 #define AO_FIFO_Mode_HF (1<<14)
262 #define AO_FIFO_Mode_E (0<<14)
263 #define AO_FIFO_Retransmit_Enable _bit13
264 #define AO_START1_Disable _bit12
265 #define AO_UC_Initial_Load_Source _bit11
266 #define AO_UC_Write_Switch _bit10
267 #define AO_UI2_Initial_Load_Source _bit9
268 #define AO_UI2_Reload_Mode _bit8
269 #define AO_UI_Initial_Load_Source _bit7
270 #define AO_UI_Reload_Mode(x) (((x) & 0x7) << 4)
271 #define AO_UI_Write_Switch _bit3
272 #define AO_BC_Initial_Load_Source _bit2
273 #define AO_BC_Reload_Mode _bit1
274 #define AO_BC_Write_Switch _bit0
275 
276 #define AO_UI_Load_A_Register 40
277 #define AO_UI_Load_A_Register_High 40
278 #define AO_UI_Load_A_Register_Low 41
279 #define AO_UI_Load_B_Register 42
280 #define AO_UI_Save_Registers 16
281 #define AO_BC_Load_A_Register 44
282 #define AO_BC_Load_A_Register_High 44
283 #define AO_BC_Load_A_Register_Low 45
284 #define AO_BC_Load_B_Register 46
285 #define AO_BC_Load_B_Register_High 46
286 #define AO_BC_Load_B_Register_Low 47
287 #define AO_BC_Save_Registers 18
288 #define AO_UC_Load_A_Register 48
289 #define AO_UC_Load_A_Register_High 48
290 #define AO_UC_Load_A_Register_Low 49
291 #define AO_UC_Load_B_Register 50
292 #define AO_UC_Save_Registers 20
293 
294 #define Clock_and_FOUT_Register 56
295 #define FOUT_Enable _bit15
296 #define FOUT_Timebase_Select _bit14
297 #define DIO_Serial_Out_Divide_By_2 _bit13
298 #define Slow_Internal_Time_Divide_By_2 _bit12
299 #define Slow_Internal_Timebase _bit11
300 #define G_Source_Divide_By_2 _bit10
301 #define Clock_To_Board_Divide_By_2 _bit9
302 #define Clock_To_Board _bit8
303 #define AI_Output_Divide_By_2 _bit7
304 #define AI_Source_Divide_By_2 _bit6
305 #define AO_Output_Divide_By_2 _bit5
306 #define AO_Source_Divide_By_2 _bit4
307 #define FOUT_Divider_mask 0xf
308 #define FOUT_Divider(x) (((x) & 0xf) << 0)
309 
310 #define IO_Bidirection_Pin_Register 57
311 #define RTSI_Trig_Direction_Register 58
312 #define Drive_RTSI_Clock_Bit 0x1
313 #define Use_RTSI_Clock_Bit 0x2
314 
315 static inline unsigned int RTSI_Output_Bit(unsigned channel, int is_mseries)
316 {
317  unsigned max_channel;
318  unsigned base_bit_shift;
319  if(is_mseries)
320  {
321  base_bit_shift = 8;
322  max_channel = 7;
323  }else
324  {
325  base_bit_shift = 9;
326  max_channel = 6;
327  }
328  if(channel > max_channel)
329  {
330  rtdm_printk("%s: bug, invalid RTSI_channel=%i\n",
331  __FUNCTION__, channel);
332  return 0;
333  }
334  return 1 << (base_bit_shift + channel);
335 }
336 
337 #define Interrupt_Control_Register 59
338 #define Interrupt_B_Enable _bit15
339 #define Interrupt_B_Output_Select(x) ((x)<<12)
340 #define Interrupt_A_Enable _bit11
341 #define Interrupt_A_Output_Select(x) ((x)<<8)
342 #define Pass_Thru_0_Interrupt_Polarity _bit3
343 #define Pass_Thru_1_Interrupt_Polarity _bit2
344 #define Interrupt_Output_On_3_Pins _bit1
345 #define Interrupt_Output_Polarity _bit0
346 
347 #define AI_Output_Control_Register 60
348 #define AI_START_Output_Select _bit10
349 #define AI_SCAN_IN_PROG_Output_Select(x) (((x) & 0x3) << 8)
350 #define AI_EXTMUX_CLK_Output_Select(x) (((x) & 0x3) << 6)
351 #define AI_LOCALMUX_CLK_Output_Select(x) ((x)<<4)
352 #define AI_SC_TC_Output_Select(x) ((x)<<2)
353 #define AI_CONVERT_Output_High_Z 0
354 #define AI_CONVERT_Output_Ground 1
355 #define AI_CONVERT_Output_Enable_Low 2
356 #define AI_CONVERT_Output_Enable_High 3
357 #define AI_CONVERT_Output_Select(x) ((x) & 0x3)
358 
359 #define AI_START_STOP_Select_Register 62
360 #define AI_START_Polarity _bit15
361 #define AI_STOP_Polarity _bit14
362 #define AI_STOP_Sync _bit13
363 #define AI_STOP_Edge _bit12
364 #define AI_STOP_Select(a) (((a) & 0x1f)<<7)
365 #define AI_START_Sync _bit6
366 #define AI_START_Edge _bit5
367 #define AI_START_Select(a) ((a) & 0x1f)
368 
369 #define AI_Trigger_Select_Register 63
370 #define AI_START1_Polarity _bit15
371 #define AI_START2_Polarity _bit14
372 #define AI_START2_Sync _bit13
373 #define AI_START2_Edge _bit12
374 #define AI_START2_Select(a) (((a) & 0x1f) << 7)
375 #define AI_START1_Sync _bit6
376 #define AI_START1_Edge _bit5
377 #define AI_START1_Select(a) ((a) & 0x1f)
378 
379 #define AI_DIV_Load_A_Register 64
380 
381 #define AO_Start_Select_Register 66
382 #define AO_UI2_Software_Gate _bit15
383 #define AO_UI2_External_Gate_Polarity _bit14
384 #define AO_START_Polarity _bit13
385 #define AO_AOFREQ_Enable _bit12
386 #define AO_UI2_External_Gate_Select(a) (((a) & 0x1f) << 7)
387 #define AO_START_Sync _bit6
388 #define AO_START_Edge _bit5
389 #define AO_START_Select(a) ((a) & 0x1f)
390 
391 #define AO_Trigger_Select_Register 67
392 #define AO_UI2_External_Gate_Enable _bit15
393 #define AO_Delayed_START1 _bit14
394 #define AO_START1_Polarity _bit13
395 #define AO_UI2_Source_Polarity _bit12
396 #define AO_UI2_Source_Select(x) (((x)&0x1f)<<7)
397 #define AO_START1_Sync _bit6
398 #define AO_START1_Edge _bit5
399 #define AO_START1_Select(x) (((x)&0x1f)<<0)
400 
401 #define AO_Mode_3_Register 70
402 #define AO_UI2_Switch_Load_Next_TC _bit13
403 #define AO_UC_Switch_Load_Every_BC_TC _bit12
404 #define AO_Trigger_Length _bit11
405 #define AO_Stop_On_Overrun_Error _bit5
406 #define AO_Stop_On_BC_TC_Trigger_Error _bit4
407 #define AO_Stop_On_BC_TC_Error _bit3
408 #define AO_Not_An_UPDATE _bit2
409 #define AO_Software_Gate _bit1
410 #define AO_Last_Gate_Disable _bit0 /* M Series only */
411 
412 #define Joint_Reset_Register 72
413 #define Software_Reset _bit11
414 #define AO_Configuration_End _bit9
415 #define AI_Configuration_End _bit8
416 #define AO_Configuration_Start _bit5
417 #define AI_Configuration_Start _bit4
418 #define G1_Reset _bit3
419 #define G0_Reset _bit2
420 #define AO_Reset _bit1
421 #define AI_Reset _bit0
422 
423 #define Interrupt_A_Enable_Register 73
424 #define Pass_Thru_0_Interrupt_Enable _bit9
425 #define G0_Gate_Interrupt_Enable _bit8
426 #define AI_FIFO_Interrupt_Enable _bit7
427 #define G0_TC_Interrupt_Enable _bit6
428 #define AI_Error_Interrupt_Enable _bit5
429 #define AI_STOP_Interrupt_Enable _bit4
430 #define AI_START_Interrupt_Enable _bit3
431 #define AI_START2_Interrupt_Enable _bit2
432 #define AI_START1_Interrupt_Enable _bit1
433 #define AI_SC_TC_Interrupt_Enable _bit0
434 
435 #define Interrupt_B_Enable_Register 75
436 #define Pass_Thru_1_Interrupt_Enable _bit11
437 #define G1_Gate_Interrupt_Enable _bit10
438 #define G1_TC_Interrupt_Enable _bit9
439 #define AO_FIFO_Interrupt_Enable _bit8
440 #define AO_UI2_TC_Interrupt_Enable _bit7
441 #define AO_UC_TC_Interrupt_Enable _bit6
442 #define AO_Error_Interrupt_Enable _bit5
443 #define AO_STOP_Interrupt_Enable _bit4
444 #define AO_START_Interrupt_Enable _bit3
445 #define AO_UPDATE_Interrupt_Enable _bit2
446 #define AO_START1_Interrupt_Enable _bit1
447 #define AO_BC_TC_Interrupt_Enable _bit0
448 
449 #define Second_IRQ_A_Enable_Register 74
450 #define AI_SC_TC_Second_Irq_Enable _bit0
451 #define AI_START1_Second_Irq_Enable _bit1
452 #define AI_START2_Second_Irq_Enable _bit2
453 #define AI_START_Second_Irq_Enable _bit3
454 #define AI_STOP_Second_Irq_Enable _bit4
455 #define AI_Error_Second_Irq_Enable _bit5
456 #define G0_TC_Second_Irq_Enable _bit6
457 #define AI_FIFO_Second_Irq_Enable _bit7
458 #define G0_Gate_Second_Irq_Enable _bit8
459 #define Pass_Thru_0_Second_Irq_Enable _bit9
460 
461 #define Second_IRQ_B_Enable_Register 76
462 #define AO_BC_TC_Second_Irq_Enable _bit0
463 #define AO_START1_Second_Irq_Enable _bit1
464 #define AO_UPDATE_Second_Irq_Enable _bit2
465 #define AO_START_Second_Irq_Enable _bit3
466 #define AO_STOP_Second_Irq_Enable _bit4
467 #define AO_Error_Second_Irq_Enable _bit5
468 #define AO_UC_TC_Second_Irq_Enable _bit6
469 #define AO_UI2_TC_Second_Irq_Enable _bit7
470 #define AO_FIFO_Second_Irq_Enable _bit8
471 #define G1_TC_Second_Irq_Enable _bit9
472 #define G1_Gate_Second_Irq_Enable _bit10
473 #define Pass_Thru_1_Second_Irq_Enable _bit11
474 
475 #define AI_Personal_Register 77
476 #define AI_SHIFTIN_Pulse_Width _bit15
477 #define AI_EOC_Polarity _bit14
478 #define AI_SOC_Polarity _bit13
479 #define AI_SHIFTIN_Polarity _bit12
480 #define AI_CONVERT_Pulse_Timebase _bit11
481 #define AI_CONVERT_Pulse_Width _bit10
482 #define AI_CONVERT_Original_Pulse _bit9
483 #define AI_FIFO_Flags_Polarity _bit8
484 #define AI_Overrun_Mode _bit7
485 #define AI_EXTMUX_CLK_Pulse_Width _bit6
486 #define AI_LOCALMUX_CLK_Pulse_Width _bit5
487 #define AI_AIFREQ_Polarity _bit4
488 
489 #define AO_Personal_Register 78
490 #define AO_Interval_Buffer_Mode _bit3
491 #define AO_BC_Source_Select _bit4
492 #define AO_UPDATE_Pulse_Width _bit5
493 #define AO_UPDATE_Pulse_Timebase _bit6
494 #define AO_UPDATE_Original_Pulse _bit7
495 #define AO_DMA_PIO_Control _bit8 /* M Series: reserved */
496 #define AO_AOFREQ_Polarity _bit9 /* M Series: reserved */
497 #define AO_FIFO_Enable _bit10
498 #define AO_FIFO_Flags_Polarity _bit11 /* M Series: reserved */
499 #define AO_TMRDACWR_Pulse_Width _bit12
500 #define AO_Fast_CPU _bit13 /* M Series: reserved */
501 #define AO_Number_Of_DAC_Packages _bit14 /* 1 for "single" mode,
502  0 for "dual" */
503 #define AO_Multiple_DACS_Per_Package _bit15 /* M Series only */
504 
505 #define RTSI_Trig_A_Output_Register 79
506 
507 #define RTSI_Trig_B_Output_Register 80
508 #define RTSI_Sub_Selection_1_Bit _bit15 /* not for M Series */
509 #define RTSI_Trig_Output_Bits(x, y) ((y & 0xf) << ((x % 4) * 4))
510 #define RTSI_Trig_Output_Mask(x) (0xf << ((x % 4) * 4))
511 #define RTSI_Trig_Output_Source(x, y) ((y >> ((x % 4) * 4)) & 0xf)
512 
513 #define RTSI_Board_Register 81
514 #define Write_Strobe_0_Register 82
515 #define Write_Strobe_1_Register 83
516 #define Write_Strobe_2_Register 84
517 #define Write_Strobe_3_Register 85
518 
519 #define AO_Output_Control_Register 86
520 #define AO_External_Gate_Enable _bit15
521 #define AO_External_Gate_Select(x) (((x)&0x1f)<<10)
522 #define AO_Number_Of_Channels(x) (((x)&0xf)<<6)
523 #define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4)
524 #define AO_External_Gate_Polarity _bit3
525 #define AO_UPDATE2_Output_Toggle _bit2
526 #define AO_Update_Output_High_Z 0
527 #define AO_Update_Output_Ground 1
528 #define AO_Update_Output_Enable_Low 2
529 #define AO_Update_Output_Enable_High 3
530 #define AO_UPDATE_Output_Select(x) (x&0x3)
531 
532 #define AI_Mode_3_Register 87
533 #define AI_Trigger_Length _bit15
534 #define AI_Delay_START _bit14
535 #define AI_Software_Gate _bit13
536 #define AI_SI_Special_Trigger_Delay _bit12
537 #define AI_SI2_Source_Select _bit11
538 #define AI_Delayed_START2 _bit10
539 #define AI_Delayed_START1 _bit9
540 #define AI_External_Gate_Mode _bit8
541 #define AI_FIFO_Mode_HF_to_E (3<<6)
542 #define AI_FIFO_Mode_F (2<<6)
543 #define AI_FIFO_Mode_HF (1<<6)
544 #define AI_FIFO_Mode_NE (0<<6)
545 #define AI_External_Gate_Polarity _bit5
546 #define AI_External_Gate_Select(a) ((a) & 0x1f)
547 
548 #define G_Autoincrement_Register(a) (68+(a))
549 #define G_Command_Register(a) (6+(a))
550 #define G_HW_Save_Register(a) (8+(a)*2)
551 #define G_HW_Save_Register_High(a) (8+(a)*2)
552 #define G_HW_Save_Register_Low(a) (9+(a)*2)
553 #define G_Input_Select_Register(a) (36+(a))
554 #define G_Load_A_Register(a) (28+(a)*4)
555 #define G_Load_A_Register_High(a) (28+(a)*4)
556 #define G_Load_A_Register_Low(a) (29+(a)*4)
557 #define G_Load_B_Register(a) (30+(a)*4)
558 #define G_Load_B_Register_High(a) (30+(a)*4)
559 #define G_Load_B_Register_Low(a) (31+(a)*4)
560 #define G_Mode_Register(a) (26+(a))
561 #define G_Save_Register(a) (12+(a)*2)
562 #define G_Save_Register_High(a) (12+(a)*2)
563 #define G_Save_Register_Low(a) (13+(a)*2)
564 #define G_Status_Register 4
565 #define Analog_Trigger_Etc_Register 61
566 
567 /* command register */
568 #define G_Disarm_Copy _bit15 /* strobe */
569 #define G_Save_Trace_Copy _bit14
570 #define G_Arm_Copy _bit13 /* strobe */
571 #define G_Bank_Switch_Start _bit10 /* strobe */
572 #define G_Little_Big_Endian _bit9
573 #define G_Synchronized_Gate _bit8
574 #define G_Write_Switch _bit7
575 #define G_Up_Down(a) (((a)&0x03)<<5)
576 #define G_Disarm _bit4 /* strobe */
577 #define G_Analog_Trigger_Reset _bit3 /* strobe */
578 #define G_Save_Trace _bit1
579 #define G_Arm _bit0 /* strobe */
580 
581 /* channel agnostic names for the command register #defines */
582 #define G_Bank_Switch_Enable _bit12
583 #define G_Bank_Switch_Mode _bit11
584 #define G_Load _bit2 /* strobe */
585 
586 /* input select register */
587 #define G_Gate_Select(a) (((a)&0x1f)<<7)
588 #define G_Source_Select(a) (((a)&0x1f)<<2)
589 #define G_Write_Acknowledges_Irq _bit1
590 #define G_Read_Acknowledges_Irq _bit0
591 
592 /* same input select register, but with channel agnostic names */
593 #define G_Source_Polarity _bit15
594 #define G_Output_Polarity _bit14
595 #define G_OR_Gate _bit13
596 #define G_Gate_Select_Load_Source _bit12
597 
598 /* mode register */
599 #define G_Loading_On_TC _bit12
600 #define G_Output_Mode(a) (((a)&0x03)<<8)
601 #define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3)
602 #define G_Gating_Mode(a) (((a)&0x03)<<0)
603 
604 /* same input mode register, but with channel agnostic names */
605 #define G_Load_Source_Select _bit7
606 #define G_Reload_Source_Switching _bit15
607 #define G_Loading_On_Gate _bit14
608 #define G_Gate_Polarity _bit13
609 
610 #define G_Counting_Once(a) (((a)&0x03)<<10)
611 #define G_Stop_Mode(a) (((a)&0x03)<<5)
612 #define G_Gate_On_Both_Edges _bit2
613 
614 /* G_Status_Register */
615 #define G1_Gate_Error_St _bit15
616 #define G0_Gate_Error_St _bit14
617 #define G1_TC_Error_St _bit13
618 #define G0_TC_Error_St _bit12
619 #define G1_No_Load_Between_Gates_St _bit11
620 #define G0_No_Load_Between_Gates_St _bit10
621 #define G1_Armed_St _bit9
622 #define G0_Armed_St _bit8
623 #define G1_Stale_Data_St _bit7
624 #define G0_Stale_Data_St _bit6
625 #define G1_Next_Load_Source_St _bit5
626 #define G0_Next_Load_Source_St _bit4
627 #define G1_Counting_St _bit3
628 #define G0_Counting_St _bit2
629 #define G1_Save_St _bit1
630 #define G0_Save_St _bit0
631 
632 /* general purpose counter timer */
633 #define G_Autoincrement(a) ((a)<<0)
634 
635 /*Analog_Trigger_Etc_Register*/
636 #define Analog_Trigger_Mode(x) ((x) & 0x7)
637 #define Analog_Trigger_Enable _bit3
638 #define Analog_Trigger_Drive _bit4
639 #define GPFO_1_Output_Select _bit7
640 #define GPFO_0_Output_Select(a) ((a)<<11)
641 #define GPFO_0_Output_Enable _bit14
642 #define GPFO_1_Output_Enable _bit15
643 
644 /* Additional windowed registers unique to E series */
645 
646 /* 16 bit registers shadowed from DAQ-STC */
647 #define Window_Address 0x00
648 #define Window_Data 0x02
649 
650 #define Configuration_Memory_Clear 82
651 #define ADC_FIFO_Clear 83
652 #define DAC_FIFO_Clear 84
653 
654 /* i/o port offsets */
655 
656 /* 8 bit registers */
657 #define XXX_Status 0x01
658 #define PROMOUT _bit0
659 #define AI_FIFO_LOWER_NOT_EMPTY _bit3
660 
661 #define Serial_Command 0x0d
662 #define Misc_Command 0x0f
663 #define Port_A 0x19
664 #define Port_B 0x1b
665 #define Port_C 0x1d
666 #define Configuration 0x1f
667 #define Strobes 0x01
668 #define Channel_A_Mode 0x03
669 #define Channel_B_Mode 0x05
670 #define Channel_C_Mode 0x07
671 #define AI_AO_Select 0x09
672 #define AI_DMA_Select_Shift 0
673 #define AI_DMA_Select_Mask 0xf
674 #define AO_DMA_Select_Shift 4
675 #define AO_DMA_Select_Mask (0xf << AO_DMA_Select_Shift)
676 
677 #define G0_G1_Select 0x0b
678 
679 static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
680 {
681  if(channel < 4) return 1 << channel;
682  if(channel == 4) return 0x3;
683  if(channel == 5) return 0x5;
684  BUG();
685  return 0;
686 }
687 static inline unsigned GPCT_DMA_Select_Bits(unsigned gpct_index, unsigned mite_channel)
688 {
689  BUG_ON(gpct_index > 1);
690  return ni_stc_dma_channel_select_bitfield(mite_channel) << (4 * gpct_index);
691 }
692 static inline unsigned GPCT_DMA_Select_Mask(unsigned gpct_index)
693 {
694  BUG_ON(gpct_index > 1);
695  return 0xf << (4 * gpct_index);
696 }
697 
698 /* 16 bit registers */
699 
700 #define Configuration_Memory_Low 0x10
701 #define AI_DITHER _bit9
702 #define AI_LAST_CHANNEL _bit15
703 
704 #define Configuration_Memory_High 0x12
705 #define AI_AC_COUPLE _bit11
706 #define AI_DIFFERENTIAL _bit12
707 #define AI_COMMON _bit13
708 #define AI_GROUND (_bit12|_bit13)
709 #define AI_CONFIG_CHANNEL(x) (x&0x3f)
710 
711 #define ADC_FIFO_Data_Register 0x1c
712 
713 #define AO_Configuration 0x16
714 #define AO_Bipolar _bit0
715 #define AO_Deglitch _bit1
716 #define AO_Ext_Ref _bit2
717 #define AO_Ground_Ref _bit3
718 #define AO_Channel(x) ((x) << 8)
719 
720 #define DAC_FIFO_Data 0x1e
721 #define DAC0_Direct_Data 0x18
722 #define DAC1_Direct_Data 0x1a
723 
724 /* 611x registers (these boards differ from the e-series) */
725 
726 #define Magic_611x 0x19 /* w8 (new) */
727 #define Calibration_Channel_Select_611x 0x1a /* w16 (new) */
728 #define ADC_FIFO_Data_611x 0x1c /* r32 (incompatible) */
729 #define AI_FIFO_Offset_Load_611x 0x05 /* r8 (new) */
730 #define DAC_FIFO_Data_611x 0x14 /* w32 (incompatible) */
731 #define Cal_Gain_Select_611x 0x05 /* w8 (new) */
732 
733 #define AO_Window_Address_611x 0x18
734 #define AO_Window_Data_611x 0x1e
735 
736 /* 6143 registers */
737 #define Magic_6143 0x19 /* w8 */
738 #define G0G1_DMA_Select_6143 0x0B /* w8 */
739 #define PipelineDelay_6143 0x1f /* w8 */
740 #define EOC_Set_6143 0x1D /* w8 */
741 #define AIDMA_Select_6143 0x09 /* w8 */
742 #define AIFIFO_Data_6143 0x8C /* w32 */
743 #define AIFIFO_Flag_6143 0x84 /* w32 */
744 #define AIFIFO_Control_6143 0x88 /* w32 */
745 #define AIFIFO_Status_6143 0x88 /* w32 */
746 #define AIFIFO_DMAThreshold_6143 0x90 /* w32 */
747 #define AIFIFO_Words_Available_6143 0x94 /* w32 */
748 
749 #define Calibration_Channel_6143 0x42 /* w16 */
750 #define Calibration_LowTime_6143 0x20 /* w16 */
751 #define Calibration_HighTime_6143 0x22 /* w16 */
752 #define Relay_Counter_Load_Val__6143 0x4C /* w32 */
753 #define Signature_6143 0x50 /* w32 */
754 #define Release_Date_6143 0x54 /* w32 */
755 #define Release_Oldest_Date_6143 0x58 /* w32 */
756 
757 #define Calibration_Channel_6143_RelayOn 0x8000 /* Calibration relay switch On */
758 #define Calibration_Channel_6143_RelayOff 0x4000 /* Calibration relay switch Off */
759 #define Calibration_Channel_Gnd_Gnd 0x00 /* Offset Calibration */
760 #define Calibration_Channel_2v5_Gnd 0x02 /* 2.5V Reference */
761 #define Calibration_Channel_Pwm_Gnd 0x05 /* +/- 5V Self Cal */
762 #define Calibration_Channel_2v5_Pwm 0x0a /* PWM Calibration */
763 #define Calibration_Channel_Pwm_Pwm 0x0d /* CMRR */
764 #define Calibration_Channel_Gnd_Pwm 0x0e /* PWM Calibration */
765 
766 /* 671x, 611x registers */
767 
768 /* 671xi 611x windowed ao registers */
769 #define AO_Immediate_671x 0x11 /* W 16 */
770 #define AO_Timed_611x 0x10 /* W 16 */
771 #define AO_FIFO_Offset_Load_611x 0x13 /* W32 */
772 #define AO_Later_Single_Point_Updates 0x14 /* W 16 */
773 #define AO_Waveform_Generation_611x 0x15 /* W 16 */
774 #define AO_Misc_611x 0x16 /* W 16 */
775 #define AO_Calibration_Channel_Select_67xx 0x17 /* W 16 */
776 #define AO_Configuration_2_67xx 0x18 /* W 16 */
777 #define CAL_ADC_Command_67xx 0x19 /* W 8 */
778 #define CAL_ADC_Status_67xx 0x1a /* R 8 */
779 #define CAL_ADC_Data_67xx 0x1b /* R 16 */
780 #define CAL_ADC_Config_Data_High_Word_67xx 0x1c /* RW 16 */
781 #define CAL_ADC_Config_Data_Low_Word_67xx 0x1d /* RW 16 */
782 
783 static inline unsigned int DACx_Direct_Data_671x(int channel)
784 {
785  return channel;
786 }
787 
788 #define CLEAR_WG _bit0
789 
790 #define CSCFG_CAL_CONTROL_MASK 0x7
791 #define CSCFG_SELF_CAL_OFFSET 0x1
792 #define CSCFG_SELF_CAL_GAIN 0x2
793 #define CSCFG_SELF_CAL_OFFSET_GAIN 0x3
794 #define CSCFG_SYSTEM_CAL_OFFSET 0x5
795 #define CSCFG_SYSTEM_CAL_GAIN 0x6
796 #define CSCFG_DONE (1 << 3)
797 #define CSCFG_POWER_SAVE_SELECT (1 << 4)
798 #define CSCFG_PORT_MODE (1 << 5)
799 #define CSCFG_RESET_VALID (1 << 6)
800 #define CSCFG_RESET (1 << 7)
801 #define CSCFG_UNIPOLAR (1 << 12)
802 #define CSCFG_WORD_RATE_2180_CYCLES (0x0 << 13)
803 #define CSCFG_WORD_RATE_1092_CYCLES (0x1 << 13)
804 #define CSCFG_WORD_RATE_532_CYCLES (0x2 << 13)
805 #define CSCFG_WORD_RATE_388_CYCLES (0x3 << 13)
806 #define CSCFG_WORD_RATE_324_CYCLES (0x4 << 13)
807 #define CSCFG_WORD_RATE_17444_CYCLES (0x5 << 13)
808 #define CSCFG_WORD_RATE_8724_CYCLES (0x6 << 13)
809 #define CSCFG_WORD_RATE_4364_CYCLES (0x7 << 13)
810 #define CSCFG_WORD_RATE_MASK (0x7 << 13)
811 #define CSCFG_LOW_POWER (1 << 16)
812 
813 #define CS5529_CONFIG_DOUT(x) (1 << (18 + x))
814 #define CS5529_CONFIG_AOUT(x) (1 << (22 + x))
815 
816 /* cs5529 command bits */
817 #define CSCMD_POWER_SAVE _bit0
818 #define CSCMD_REGISTER_SELECT_MASK 0xe
819 #define CSCMD_OFFSET_REGISTER 0x0
820 #define CSCMD_GAIN_REGISTER _bit1
821 #define CSCMD_CONFIG_REGISTER _bit2
822 #define CSCMD_READ _bit4
823 #define CSCMD_CONTINUOUS_CONVERSIONS _bit5
824 #define CSCMD_SINGLE_CONVERSION _bit6
825 #define CSCMD_COMMAND _bit7
826 
827 /* cs5529 status bits */
828 #define CSS_ADC_BUSY _bit0
829 #define CSS_OSC_DETECT _bit1 /* indicates adc error */
830 #define CSS_OVERRANGE _bit3
831 
832 #define SerDacLd(x) (0x08<<(x))
833 
834 /*
835  This is stuff unique to the NI E series drivers,
836  but I thought I'd put it here anyway.
837 */
838 
839 enum
840 {
841  ai_gain_16 = 0,
842  ai_gain_8,
843  ai_gain_14,
844  ai_gain_4,
845  ai_gain_611x,
846  ai_gain_622x,
847  ai_gain_628x,
848  ai_gain_6143
849 };
850 enum caldac_enum
851 {
852  caldac_none=0,
853  mb88341,
854  dac8800,
855  dac8043,
856  ad8522,
857  ad8804,
858  ad8842,
859  ad8804_debug
860 };
861 enum ni_reg_type
862 {
863  ni_reg_normal = 0x0,
864  ni_reg_611x = 0x1,
865  ni_reg_6711 = 0x2,
866  ni_reg_6713 = 0x4,
867  ni_reg_67xx_mask = 0x6,
868  ni_reg_6xxx_mask = 0x7,
869  ni_reg_622x = 0x8,
870  ni_reg_625x = 0x10,
871  ni_reg_628x = 0x18,
872  ni_reg_m_series_mask = 0x18,
873  ni_reg_6143 = 0x20
874 };
875 
876 /* M Series registers offsets */
877 #define M_Offset_CDIO_DMA_Select 0x7 /* write */
878 #define M_Offset_SCXI_Status 0x7 /* read */
879 #define M_Offset_AI_AO_Select 0x9 /* write, same offset as e-series */
880 #define M_Offset_SCXI_Serial_Data_In 0x9 /* read */
881 #define M_Offset_G0_G1_Select 0xb /* write, same offset as e-series */
882 #define M_Offset_Misc_Command 0xf
883 #define M_Offset_SCXI_Serial_Data_Out 0x11
884 #define M_Offset_SCXI_Control 0x13
885 #define M_Offset_SCXI_Output_Enable 0x15
886 #define M_Offset_AI_FIFO_Data 0x1c
887 #define M_Offset_Static_Digital_Output 0x24 /* write */
888 #define M_Offset_Static_Digital_Input 0x24 /* read */
889 #define M_Offset_DIO_Direction 0x28
890 #define M_Offset_Cal_PWM 0x40
891 #define M_Offset_AI_Config_FIFO_Data 0x5e
892 #define M_Offset_Interrupt_C_Enable 0x88 /* write */
893 #define M_Offset_Interrupt_C_Status 0x88 /* read */
894 #define M_Offset_Analog_Trigger_Control 0x8c
895 #define M_Offset_AO_Serial_Interrupt_Enable 0xa0
896 #define M_Offset_AO_Serial_Interrupt_Ack 0xa1 /* write */
897 #define M_Offset_AO_Serial_Interrupt_Status 0xa1 /* read */
898 #define M_Offset_AO_Calibration 0xa3
899 #define M_Offset_AO_FIFO_Data 0xa4
900 #define M_Offset_PFI_Filter 0xb0
901 #define M_Offset_RTSI_Filter 0xb4
902 #define M_Offset_SCXI_Legacy_Compatibility 0xbc
903 #define M_Offset_Interrupt_A_Ack 0x104 /* write */
904 #define M_Offset_AI_Status_1 0x104 /* read */
905 #define M_Offset_Interrupt_B_Ack 0x106 /* write */
906 #define M_Offset_AO_Status_1 0x106 /* read */
907 #define M_Offset_AI_Command_2 0x108 /* write */
908 #define M_Offset_G01_Status 0x108 /* read */
909 #define M_Offset_AO_Command_2 0x10a
910 #define M_Offset_AO_Status_2 0x10c /* read */
911 #define M_Offset_G0_Command 0x10c /* write */
912 #define M_Offset_G1_Command 0x10e /* write */
913 #define M_Offset_G0_HW_Save 0x110
914 #define M_Offset_G0_HW_Save_High 0x110
915 #define M_Offset_AI_Command_1 0x110
916 #define M_Offset_G0_HW_Save_Low 0x112
917 #define M_Offset_AO_Command_1 0x112
918 #define M_Offset_G1_HW_Save 0x114
919 #define M_Offset_G1_HW_Save_High 0x114
920 #define M_Offset_G1_HW_Save_Low 0x116
921 #define M_Offset_AI_Mode_1 0x118
922 #define M_Offset_G0_Save 0x118
923 #define M_Offset_G0_Save_High 0x118
924 #define M_Offset_AI_Mode_2 0x11a
925 #define M_Offset_G0_Save_Low 0x11a
926 #define M_Offset_AI_SI_Load_A 0x11c
927 #define M_Offset_G1_Save 0x11c
928 #define M_Offset_G1_Save_High 0x11c
929 #define M_Offset_G1_Save_Low 0x11e
930 #define M_Offset_AI_SI_Load_B 0x120 /* write */
931 #define M_Offset_AO_UI_Save 0x120 /* read */
932 #define M_Offset_AI_SC_Load_A 0x124 /* write */
933 #define M_Offset_AO_BC_Save 0x124 /* read */
934 #define M_Offset_AI_SC_Load_B 0x128 /* write */
935 #define M_Offset_AO_UC_Save 0x128 /* read */
936 #define M_Offset_AI_SI2_Load_A 0x12c
937 #define M_Offset_AI_SI2_Load_B 0x130
938 #define M_Offset_G0_Mode 0x134
939 #define M_Offset_G1_Mode 0x136 /* write */
940 #define M_Offset_Joint_Status_1 0x136 /* read */
941 #define M_Offset_G0_Load_A 0x138
942 #define M_Offset_Joint_Status_2 0x13a
943 #define M_Offset_G0_Load_B 0x13c
944 #define M_Offset_G1_Load_A 0x140
945 #define M_Offset_G1_Load_B 0x144
946 #define M_Offset_G0_Input_Select 0x148
947 #define M_Offset_G1_Input_Select 0x14a
948 #define M_Offset_AO_Mode_1 0x14c
949 #define M_Offset_AO_Mode_2 0x14e
950 #define M_Offset_AO_UI_Load_A 0x150
951 #define M_Offset_AO_UI_Load_B 0x154
952 #define M_Offset_AO_BC_Load_A 0x158
953 #define M_Offset_AO_BC_Load_B 0x15c
954 #define M_Offset_AO_UC_Load_A 0x160
955 #define M_Offset_AO_UC_Load_B 0x164
956 #define M_Offset_Clock_and_FOUT 0x170
957 #define M_Offset_IO_Bidirection_Pin 0x172
958 #define M_Offset_RTSI_Trig_Direction 0x174
959 #define M_Offset_Interrupt_Control 0x176
960 #define M_Offset_AI_Output_Control 0x178
961 #define M_Offset_Analog_Trigger_Etc 0x17a
962 #define M_Offset_AI_START_STOP_Select 0x17c
963 #define M_Offset_AI_Trigger_Select 0x17e
964 #define M_Offset_AI_SI_Save 0x180 /* read */
965 #define M_Offset_AI_DIV_Load_A 0x180 /* write */
966 #define M_Offset_AI_SC_Save 0x184 /* read */
967 #define M_Offset_AO_Start_Select 0x184 /* write */
968 #define M_Offset_AO_Trigger_Select 0x186
969 #define M_Offset_AO_Mode_3 0x18c
970 #define M_Offset_G0_Autoincrement 0x188
971 #define M_Offset_G1_Autoincrement 0x18a
972 #define M_Offset_Joint_Reset 0x190
973 #define M_Offset_Interrupt_A_Enable 0x192
974 #define M_Offset_Interrupt_B_Enable 0x196
975 #define M_Offset_AI_Personal 0x19a
976 #define M_Offset_AO_Personal 0x19c
977 #define M_Offset_RTSI_Trig_A_Output 0x19e
978 #define M_Offset_RTSI_Trig_B_Output 0x1a0
979 #define M_Offset_RTSI_Shared_MUX 0x1a2
980 #define M_Offset_AO_Output_Control 0x1ac
981 #define M_Offset_AI_Mode_3 0x1ae
982 #define M_Offset_Configuration_Memory_Clear 0x1a4
983 #define M_Offset_AI_FIFO_Clear 0x1a6
984 #define M_Offset_AO_FIFO_Clear 0x1a8
985 #define M_Offset_G0_Counting_Mode 0x1b0
986 #define M_Offset_G1_Counting_Mode 0x1b2
987 #define M_Offset_G0_Second_Gate 0x1b4
988 #define M_Offset_G1_Second_Gate 0x1b6
989 #define M_Offset_G0_DMA_Config 0x1b8 /* write */
990 #define M_Offset_G0_DMA_Status 0x1b8 /* read */
991 #define M_Offset_G1_DMA_Config 0x1ba /* write */
992 #define M_Offset_G1_DMA_Status 0x1ba /* read */
993 #define M_Offset_G0_MSeries_ABZ 0x1c0
994 #define M_Offset_G1_MSeries_ABZ 0x1c2
995 #define M_Offset_Clock_and_Fout2 0x1c4
996 #define M_Offset_PLL_Control 0x1c6
997 #define M_Offset_PLL_Status 0x1c8
998 #define M_Offset_PFI_Output_Select_1 0x1d0
999 #define M_Offset_PFI_Output_Select_2 0x1d2
1000 #define M_Offset_PFI_Output_Select_3 0x1d4
1001 #define M_Offset_PFI_Output_Select_4 0x1d6
1002 #define M_Offset_PFI_Output_Select_5 0x1d8
1003 #define M_Offset_PFI_Output_Select_6 0x1da
1004 #define M_Offset_PFI_DI 0x1dc
1005 #define M_Offset_PFI_DO 0x1de
1006 #define M_Offset_AI_Config_FIFO_Bypass 0x218
1007 #define M_Offset_SCXI_DIO_Enable 0x21c
1008 #define M_Offset_CDI_FIFO_Data 0x220 /* read */
1009 #define M_Offset_CDO_FIFO_Data 0x220 /* write */
1010 #define M_Offset_CDIO_Status 0x224 /* read */
1011 #define M_Offset_CDIO_Command 0x224 /* write */
1012 #define M_Offset_CDI_Mode 0x228
1013 #define M_Offset_CDO_Mode 0x22c
1014 #define M_Offset_CDI_Mask_Enable 0x230
1015 #define M_Offset_CDO_Mask_Enable 0x234
1016 #define M_Offset_AO_Waveform_Order(x) (0xc2 + 0x4 * x)
1017 #define M_Offset_AO_Config_Bank(x) (0xc3 + 0x4 * x)
1018 #define M_Offset_DAC_Direct_Data(x) (0xc0 + 0x4 * x)
1019 #define M_Offset_Gen_PWM(x) (0x44 + 0x2 * x)
1020 
1021 static inline int M_Offset_Static_AI_Control(int i)
1022 {
1023  int offset[] =
1024  {
1025  0x64,
1026  0x261,
1027  0x262,
1028  0x263,
1029  };
1030  if(((unsigned)i) >= sizeof(offset) / sizeof(offset[0]))
1031  {
1032  rtdm_printk("%s: invalid channel=%i\n", __FUNCTION__, i);
1033  return offset[0];
1034  }
1035  return offset[i];
1036 };
1037 static inline int M_Offset_AO_Reference_Attenuation(int channel)
1038 {
1039  int offset[] =
1040  {
1041  0x264,
1042  0x265,
1043  0x266,
1044  0x267
1045  };
1046  if(((unsigned)channel) >= sizeof(offset) / sizeof(offset[0]))
1047  {
1048  rtdm_printk("%s: invalid channel=%i\n", __FUNCTION__, channel);
1049  return offset[0];
1050  }
1051  return offset[channel];
1052 };
1053 static inline unsigned M_Offset_PFI_Output_Select(unsigned n)
1054 {
1055  if(n < 1 || n > NUM_PFI_OUTPUT_SELECT_REGS)
1056  {
1057  rtdm_printk("%s: invalid pfi output select register=%i\n", __FUNCTION__, n);
1058  return M_Offset_PFI_Output_Select_1;
1059  }
1060  return M_Offset_PFI_Output_Select_1 + (n - 1) * 2;
1061 }
1062 
1063 #define MSeries_AI_Config_Channel_Type_Mask (0x7 << 6)
1064 #define MSeries_AI_Config_Channel_Type_Calibration_Bits 0x0
1065 #define MSeries_AI_Config_Channel_Type_Differential_Bits (0x1 << 6)
1066 #define MSeries_AI_Config_Channel_Type_Common_Ref_Bits (0x2 << 6)
1067 #define MSeries_AI_Config_Channel_Type_Ground_Ref_Bits (0x3 << 6)
1068 #define MSeries_AI_Config_Channel_Type_Aux_Bits (0x5 << 6)
1069 #define MSeries_AI_Config_Channel_Type_Ghost_Bits (0x7 << 6)
1070 #define MSeries_AI_Config_Polarity_Bit 0x1000 /* 0 for 2's complement encoding */
1071 #define MSeries_AI_Config_Dither_Bit 0x2000
1072 #define MSeries_AI_Config_Last_Channel_Bit 0x4000
1073 #define MSeries_AI_Config_Channel_Bits(x) (x & 0xf)
1074 #define MSeries_AI_Config_Gain_Bits(x) ((x & 0x7) << 9)
1075 
1076 static inline
1077 unsigned int MSeries_AI_Config_Bank_Bits(unsigned int reg_type,
1078  unsigned int channel)
1079 {
1080  unsigned int bits = channel & 0x30;
1081  if (reg_type == ni_reg_622x) {
1082  if (channel & 0x40)
1083  bits |= 0x400;
1084  }
1085  return bits;
1086 }
1087 
1088 #define MSeries_PLL_In_Source_Select_RTSI0_Bits 0xb
1089 #define MSeries_PLL_In_Source_Select_Star_Trigger_Bits 0x14
1090 #define MSeries_PLL_In_Source_Select_RTSI7_Bits 0x1b
1091 #define MSeries_PLL_In_Source_Select_PXI_Clock10 0x1d
1092 #define MSeries_PLL_In_Source_Select_Mask 0x1f
1093 #define MSeries_Timebase1_Select_Bit 0x20 /* use PLL for timebase 1 */
1094 #define MSeries_Timebase3_Select_Bit 0x40 /* use PLL for timebase 3 */
1095 /* Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
1096  to have no effect, at least on pxi-6281, which always uses
1097  20MHz rtsi clock frequency */
1098 #define MSeries_RTSI_10MHz_Bit 0x80
1099 
1100 static inline
1101 unsigned int MSeries_PLL_In_Source_Select_RTSI_Bits(unsigned int RTSI_channel)
1102 {
1103  if(RTSI_channel > 7)
1104  {
1105  rtdm_printk("%s: bug, invalid RTSI_channel=%i\n", __FUNCTION__, RTSI_channel);
1106  return 0;
1107  }
1108  if(RTSI_channel == 7) return MSeries_PLL_In_Source_Select_RTSI7_Bits;
1109  else return MSeries_PLL_In_Source_Select_RTSI0_Bits + RTSI_channel;
1110 }
1111 
1112 #define MSeries_PLL_Enable_Bit 0x1000
1113 #define MSeries_PLL_VCO_Mode_200_325MHz_Bits 0x0
1114 #define MSeries_PLL_VCO_Mode_175_225MHz_Bits 0x2000
1115 #define MSeries_PLL_VCO_Mode_100_225MHz_Bits 0x4000
1116 #define MSeries_PLL_VCO_Mode_75_150MHz_Bits 0x6000
1117 
1118 static inline
1119 unsigned int MSeries_PLL_Divisor_Bits(unsigned int divisor)
1120 {
1121  static const unsigned int max_divisor = 0x10;
1122  if(divisor < 1 || divisor > max_divisor)
1123  {
1124  rtdm_printk("%s: bug, invalid divisor=%i\n", __FUNCTION__, divisor);
1125  return 0;
1126  }
1127  return (divisor & 0xf) << 8;
1128 }
1129 static inline
1130 unsigned int MSeries_PLL_Multiplier_Bits(unsigned int multiplier)
1131 {
1132  static const unsigned int max_multiplier = 0x100;
1133  if(multiplier < 1 || multiplier > max_multiplier)
1134  {
1135  rtdm_printk("%s: bug, invalid multiplier=%i\n", __FUNCTION__, multiplier);
1136  return 0;
1137  }
1138  return multiplier & 0xff;
1139 }
1140 
1141 #define MSeries_PLL_Locked_Bit 0x1
1142 
1143 #define MSeries_AI_Bypass_Channel_Mask 0x7
1144 #define MSeries_AI_Bypass_Bank_Mask 0x78
1145 #define MSeries_AI_Bypass_Cal_Sel_Pos_Mask 0x380
1146 #define MSeries_AI_Bypass_Cal_Sel_Neg_Mask 0x1c00
1147 #define MSeries_AI_Bypass_Mode_Mux_Mask 0x6000
1148 #define MSeries_AO_Bypass_AO_Cal_Sel_Mask 0x38000
1149 #define MSeries_AI_Bypass_Gain_Mask 0x1c0000
1150 #define MSeries_AI_Bypass_Dither_Bit 0x200000
1151 #define MSeries_AI_Bypass_Polarity_Bit 0x400000 /* 0 for 2's complement encoding */
1152 #define MSeries_AI_Bypass_Config_FIFO_Bit 0x80000000
1153 #define MSeries_AI_Bypass_Cal_Sel_Pos_Bits(x) ((x << 7) & \
1154  MSeries_AI_Bypass_Cal_Sel_Pos_Mask)
1155 #define MSeries_AI_Bypass_Cal_Sel_Neg_Bits(x) ((x << 10) & \
1156  MSeries_AI_Bypass_Cal_Sel_Pos_Mask)
1157 #define MSeries_AI_Bypass_Gain_Bits(x) ((x << 18) & \
1158  MSeries_AI_Bypass_Gain_Mask)
1159 
1160 #define MSeries_AO_DAC_Offset_Select_Mask 0x7
1161 #define MSeries_AO_DAC_Offset_0V_Bits 0x0
1162 #define MSeries_AO_DAC_Offset_5V_Bits 0x1
1163 #define MSeries_AO_DAC_Reference_Mask 0x38
1164 #define MSeries_AO_DAC_Reference_10V_Internal_Bits 0x0
1165 #define MSeries_AO_DAC_Reference_5V_Internal_Bits 0x8
1166 #define MSeries_AO_Update_Timed_Bit 0x40
1167 #define MSeries_AO_Bipolar_Bit 0x80 /* turns on 2's complement encoding */
1168 
1169 #define MSeries_Attenuate_x5_Bit 0x1
1170 
1171 #define MSeries_Cal_PWM_High_Time_Bits(x) ((x << 16) & 0xffff0000)
1172 #define MSeries_Cal_PWM_Low_Time_Bits(x) (x & 0xffff)
1173 
1174 #define MSeries_PFI_Output_Select_Mask(x) (0x1f << (x % 3) * 5)
1175 #define MSeries_PFI_Output_Select_Bits(x, y) ((y & 0x1f) << ((x % 3) * 5))
1176 // inverse to MSeries_PFI_Output_Select_Bits
1177 #define MSeries_PFI_Output_Select_Source(x, y) ((y >> ((x % 3) * 5)) & 0x1f)
1178 
1179 #define Gi_DMA_BankSW_Error_Bit 0x10
1180 #define Gi_DMA_Reset_Bit 0x8
1181 #define Gi_DMA_Int_Enable_Bit 0x4
1182 #define Gi_DMA_Write_Bit 0x2
1183 #define Gi_DMA_Enable_Bit 0x1
1184 
1185 #define MSeries_PFI_Filter_Select_Mask(x) (0x3 << (x * 2))
1186 #define MSeries_PFI_Filter_Select_Bits(x, y) ((y << (x * 2)) & \
1187  MSeries_PFI_Filter_Select_Mask(x))
1188 
1189 /* CDIO DMA select bits */
1190 #define CDI_DMA_Select_Shift 0
1191 #define CDI_DMA_Select_Mask 0xf
1192 #define CDO_DMA_Select_Shift 4
1193 #define CDO_DMA_Select_Mask 0xf << CDO_DMA_Select_Shift
1194 
1195 /* CDIO status bits */
1196 #define CDO_FIFO_Empty_Bit 0x1
1197 #define CDO_FIFO_Full_Bit 0x2
1198 #define CDO_FIFO_Request_Bit 0x4
1199 #define CDO_Overrun_Bit 0x8
1200 #define CDO_Underflow_Bit 0x10
1201 #define CDI_FIFO_Empty_Bit 0x10000
1202 #define CDI_FIFO_Full_Bit 0x20000
1203 #define CDI_FIFO_Request_Bit 0x40000
1204 #define CDI_Overrun_Bit 0x80000
1205 #define CDI_Overflow_Bit 0x100000
1206 
1207 /* CDIO command bits */
1208 #define CDO_Disarm_Bit 0x1
1209 #define CDO_Arm_Bit 0x2
1210 #define CDI_Disarm_Bit 0x4
1211 #define CDI_Arm_Bit 0x8
1212 #define CDO_Reset_Bit 0x10
1213 #define CDI_Reset_Bit 0x20
1214 #define CDO_Error_Interrupt_Enable_Set_Bit 0x40
1215 #define CDO_Error_Interrupt_Enable_Clear_Bit 0x80
1216 #define CDI_Error_Interrupt_Enable_Set_Bit 0x100
1217 #define CDI_Error_Interrupt_Enable_Clear_Bit 0x200
1218 #define CDO_FIFO_Request_Interrupt_Enable_Set_Bit 0x400
1219 #define CDO_FIFO_Request_Interrupt_Enable_Clear_Bit 0x800
1220 #define CDI_FIFO_Request_Interrupt_Enable_Set_Bit 0x1000
1221 #define CDI_FIFO_Request_Interrupt_Enable_Clear_Bit 0x2000
1222 #define CDO_Error_Interrupt_Confirm_Bit 0x4000
1223 #define CDI_Error_Interrupt_Confirm_Bit 0x8000
1224 #define CDO_Empty_FIFO_Interrupt_Enable_Set_Bit 0x10000
1225 #define CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit 0x20000
1226 #define CDO_SW_Update_Bit 0x80000
1227 #define CDI_SW_Update_Bit 0x100000
1228 
1229 /* CDIO mode bits */
1230 #define CDI_Sample_Source_Select_Mask 0x3f
1231 #define CDI_Halt_On_Error_Bit 0x200
1232 /* sample clock on falling edge */
1233 #define CDI_Polarity_Bit 0x400
1234 /* set for half full mode, clear for not empty mode */
1235 #define CDI_FIFO_Mode_Bit 0x800
1236 /* data lanes specify which dio channels map to byte or word accesses
1237  to the dio fifos */
1238 #define CDI_Data_Lane_Mask 0x3000
1239 #define CDI_Data_Lane_0_15_Bits 0x0
1240 #define CDI_Data_Lane_16_31_Bits 0x1000
1241 #define CDI_Data_Lane_0_7_Bits 0x0
1242 #define CDI_Data_Lane_8_15_Bits 0x1000
1243 #define CDI_Data_Lane_16_23_Bits 0x2000
1244 #define CDI_Data_Lane_24_31_Bits 0x3000
1245 
1246 /* CDO mode bits */
1247 #define CDO_Sample_Source_Select_Mask 0x3f
1248 #define CDO_Retransmit_Bit 0x100
1249 #define CDO_Halt_On_Error_Bit 0x200
1250 /* sample clock on falling edge */
1251 #define CDO_Polarity_Bit 0x400
1252 /* set for half full mode, clear for not full mode */
1253 #define CDO_FIFO_Mode_Bit 0x800
1254 /* data lanes specify which dio channels map to byte or word accesses
1255  to the dio fifos */
1256 #define CDO_Data_Lane_Mask 0x3000
1257 #define CDO_Data_Lane_0_15_Bits 0x0
1258 #define CDO_Data_Lane_16_31_Bits 0x1000
1259 #define CDO_Data_Lane_0_7_Bits 0x0
1260 #define CDO_Data_Lane_8_15_Bits 0x1000
1261 #define CDO_Data_Lane_16_23_Bits 0x2000
1262 #define CDO_Data_Lane_24_31_Bits 0x3000
1263 
1264 /* Interrupt C bits */
1265 #define Interrupt_Group_C_Enable_Bit 0x1
1266 #define Interrupt_Group_C_Status_Bit 0x1
1267 
1268 #define M_SERIES_EEPROM_SIZE 1024
1269 
1270 typedef struct ni_board_struct{
1271  unsigned short device_id;
1272  int isapnp_id;
1273  char *name;
1274 
1275  int n_adchan;
1276  int adbits;
1277 
1278  int ai_fifo_depth;
1279  unsigned int alwaysdither : 1;
1280  int gainlkup;
1281  int ai_speed;
1282 
1283  int n_aochan;
1284  int aobits;
1285  struct a4l_rngdesc *ao_range_table;
1286  int ao_fifo_depth;
1287 
1288  unsigned ao_speed;
1289 
1290  unsigned num_p0_dio_channels;
1291 
1292  int reg_type;
1293  unsigned int ao_unipolar : 1;
1294  unsigned int has_8255 : 1;
1295  unsigned int has_analog_trig : 1;
1296 
1297  enum caldac_enum caldac[3];
1298 } ni_board;
1299 
1300 #define n_ni_boards (sizeof(ni_boards)/sizeof(ni_board))
1301 
1302 #define MAX_N_CALDACS 34
1303 #define MAX_N_AO_CHAN 8
1304 #define NUM_GPCT 2
1305 
1306 #define NI_PRIVATE_COMMON \
1307  uint16_t (*stc_readw)(struct a4l_device *dev, int register); \
1308  uint32_t (*stc_readl)(struct a4l_device *dev, int register); \
1309  void (*stc_writew)(struct a4l_device *dev, uint16_t value, int register); \
1310  void (*stc_writel)(struct a4l_device *dev, uint32_t value, int register); \
1311  \
1312  int dio_state; \
1313  int pfi_state; \
1314  int io_bits; \
1315  unsigned short dio_output; \
1316  unsigned short dio_control; \
1317  int ao0p,ao1p; \
1318  int lastchan; \
1319  int last_do; \
1320  int rt_irq; \
1321  int irq_polarity; \
1322  int irq_pin; \
1323  int aimode; \
1324  int ai_continuous; \
1325  int blocksize; \
1326  int n_left; \
1327  unsigned int ai_calib_source; \
1328  unsigned int ai_calib_source_enabled; \
1329  rtdm_lock_t window_lock; \
1330  rtdm_lock_t soft_reg_copy_lock; \
1331  rtdm_lock_t mite_channel_lock; \
1332  \
1333  int changain_state; \
1334  unsigned int changain_spec; \
1335  \
1336  unsigned int caldac_maxdata_list[MAX_N_CALDACS]; \
1337  unsigned short ao[MAX_N_AO_CHAN]; \
1338  unsigned short caldacs[MAX_N_CALDACS]; \
1339  \
1340  unsigned short ai_cmd2; \
1341  \
1342  unsigned short ao_conf[MAX_N_AO_CHAN]; \
1343  unsigned short ao_mode1; \
1344  unsigned short ao_mode2; \
1345  unsigned short ao_mode3; \
1346  unsigned short ao_cmd1; \
1347  unsigned short ao_cmd2; \
1348  unsigned short ao_cmd3; \
1349  unsigned short ao_trigger_select; \
1350  \
1351  struct ni_gpct_device *counter_dev; \
1352  unsigned short an_trig_etc_reg; \
1353  \
1354  unsigned ai_offset[512]; \
1355  \
1356  unsigned long serial_interval_ns; \
1357  unsigned char serial_hw_mode; \
1358  unsigned short clock_and_fout; \
1359  unsigned short clock_and_fout2; \
1360  \
1361  unsigned short int_a_enable_reg; \
1362  unsigned short int_b_enable_reg; \
1363  unsigned short io_bidirection_pin_reg; \
1364  unsigned short rtsi_trig_direction_reg; \
1365  unsigned short rtsi_trig_a_output_reg; \
1366  unsigned short rtsi_trig_b_output_reg; \
1367  unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS]; \
1368  unsigned short ai_ao_select_reg; \
1369  unsigned short g0_g1_select_reg; \
1370  unsigned short cdio_dma_select_reg; \
1371  \
1372  unsigned clock_ns; \
1373  unsigned clock_source; \
1374  \
1375  unsigned short atrig_mode; \
1376  unsigned short atrig_high; \
1377  unsigned short atrig_low; \
1378  \
1379  unsigned short pwm_up_count; \
1380  unsigned short pwm_down_count; \
1381  \
1382  sampl_t ai_fifo_buffer[0x2000]; \
1383  uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE]; \
1384  \
1385  struct mite_struct *mite; \
1386  struct mite_channel *ai_mite_chan; \
1387  struct mite_channel *ao_mite_chan;\
1388  struct mite_channel *cdo_mite_chan;\
1389  struct mite_dma_descriptor_ring *ai_mite_ring; \
1390  struct mite_dma_descriptor_ring *ao_mite_ring; \
1391  struct mite_dma_descriptor_ring *cdo_mite_ring; \
1392  struct mite_dma_descriptor_ring *gpct_mite_ring[NUM_GPCT]; \
1393  subd_8255_t subd_8255
1394 
1395 
1396 typedef struct {
1397  ni_board *board_ptr;
1398  NI_PRIVATE_COMMON;
1399 } ni_private;
1400 
1401 #define devpriv ((ni_private *)dev->priv)
1402 #define boardtype (*(ni_board *)devpriv->board_ptr)
1403 
1404 /* How we access registers */
1405 
1406 #define ni_writel(a,b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1407 #define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a)))
1408 #define ni_writew(a,b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1409 #define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a)))
1410 #define ni_writeb(a,b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1411 #define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a)))
1412 
1413 /* INSN_CONFIG_SET_CLOCK_SRC argument for NI cards */
1414 #define NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC 0 /* 10 MHz */
1415 #define NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC 1 /* 100 KHz */
1416 
1417 #endif /* _ANALOGY_NI_STC_H */
void rtdm_printk(const char *format,...)
Real-time safe message printing on kernel console.