Xenomai  3.0.8
rt_mpc52xx_fec.h
1 /*
2  * arch/ppc/5xxx_io/fec.h
3  *
4  * Header file for the MPC5xxx Fast Ethernet Controller driver
5  *
6  * Author: Dale Farnsworth <dfarnsworth@mvista.com>
7  *
8  * Copyright 2003 MontaVista Software
9  *
10  * 2003 (c) MontaVista, Software, Inc. This file is licensed under the terms
11  * of the GNU General Public License version 2. This program is licensed
12  * "as is" without any warranty of any kind, whether express or implied.
13  */
14 
15 #ifndef __RT_MPC52XX_FEC_H_
16 #define __RT_MPC52XX_FEC_H_
17 
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/spinlock.h>
21 #include <linux/mii.h>
22 #include <linux/skbuff.h>
23 #include <asm/mpc5xxx.h>
24 #include <bestcomm_api.h>
25 
26 /* Define board specific options */
27 #define CONFIG_XENO_DRIVERS_NET_USE_MDIO
28 #define CONFIG_XENO_DRIVERS_NET_FEC_GENERIC_PHY
29 #define CONFIG_XENO_DRIVERS_NET_FEC_LXT971
30 #undef CONFIG_XENO_DRIVERS_NET_FEC_DP83847
31 
32 /* Tunable constants */
33 #define MPC5xxx_FEC_RECV_BUFFER_SIZE 1518 /* max receive packet size */
34 #define MPC5xxx_FEC_RECV_BUFFER_SIZE_BC 2048 /* max receive packet size */
35 #define MPC5xxx_FEC_TBD_NUM 256 /* max transmit packets */
36 #define MPC5xxx_FEC_RBD_NUM 256 /* max receive packets */
37 
38 struct mpc5xxx_fec {
39  volatile u32 fec_id; /* FEC + 0x000 */
40  volatile u32 ievent; /* FEC + 0x004 */
41  volatile u32 imask; /* FEC + 0x008 */
42 
43  volatile u32 reserved0[1]; /* FEC + 0x00C */
44  volatile u32 r_des_active; /* FEC + 0x010 */
45  volatile u32 x_des_active; /* FEC + 0x014 */
46  volatile u32 r_des_active_cl; /* FEC + 0x018 */
47  volatile u32 x_des_active_cl; /* FEC + 0x01C */
48  volatile u32 ivent_set; /* FEC + 0x020 */
49  volatile u32 ecntrl; /* FEC + 0x024 */
50 
51  volatile u32 reserved1[6]; /* FEC + 0x028-03C */
52  volatile u32 mii_data; /* FEC + 0x040 */
53  volatile u32 mii_speed; /* FEC + 0x044 */
54  volatile u32 mii_status; /* FEC + 0x048 */
55 
56  volatile u32 reserved2[5]; /* FEC + 0x04C-05C */
57  volatile u32 mib_data; /* FEC + 0x060 */
58  volatile u32 mib_control; /* FEC + 0x064 */
59 
60  volatile u32 reserved3[6]; /* FEC + 0x068-7C */
61  volatile u32 r_activate; /* FEC + 0x080 */
62  volatile u32 r_cntrl; /* FEC + 0x084 */
63  volatile u32 r_hash; /* FEC + 0x088 */
64  volatile u32 r_data; /* FEC + 0x08C */
65  volatile u32 ar_done; /* FEC + 0x090 */
66  volatile u32 r_test; /* FEC + 0x094 */
67  volatile u32 r_mib; /* FEC + 0x098 */
68  volatile u32 r_da_low; /* FEC + 0x09C */
69  volatile u32 r_da_high; /* FEC + 0x0A0 */
70 
71  volatile u32 reserved4[7]; /* FEC + 0x0A4-0BC */
72  volatile u32 x_activate; /* FEC + 0x0C0 */
73  volatile u32 x_cntrl; /* FEC + 0x0C4 */
74  volatile u32 backoff; /* FEC + 0x0C8 */
75  volatile u32 x_data; /* FEC + 0x0CC */
76  volatile u32 x_status; /* FEC + 0x0D0 */
77  volatile u32 x_mib; /* FEC + 0x0D4 */
78  volatile u32 x_test; /* FEC + 0x0D8 */
79  volatile u32 fdxfc_da1; /* FEC + 0x0DC */
80  volatile u32 fdxfc_da2; /* FEC + 0x0E0 */
81  volatile u32 paddr1; /* FEC + 0x0E4 */
82  volatile u32 paddr2; /* FEC + 0x0E8 */
83  volatile u32 op_pause; /* FEC + 0x0EC */
84 
85  volatile u32 reserved5[4]; /* FEC + 0x0F0-0FC */
86  volatile u32 instr_reg; /* FEC + 0x100 */
87  volatile u32 context_reg; /* FEC + 0x104 */
88  volatile u32 test_cntrl; /* FEC + 0x108 */
89  volatile u32 acc_reg; /* FEC + 0x10C */
90  volatile u32 ones; /* FEC + 0x110 */
91  volatile u32 zeros; /* FEC + 0x114 */
92  volatile u32 iaddr1; /* FEC + 0x118 */
93  volatile u32 iaddr2; /* FEC + 0x11C */
94  volatile u32 gaddr1; /* FEC + 0x120 */
95  volatile u32 gaddr2; /* FEC + 0x124 */
96  volatile u32 random; /* FEC + 0x128 */
97  volatile u32 rand1; /* FEC + 0x12C */
98  volatile u32 tmp; /* FEC + 0x130 */
99 
100  volatile u32 reserved6[3]; /* FEC + 0x134-13C */
101  volatile u32 fifo_id; /* FEC + 0x140 */
102  volatile u32 x_wmrk; /* FEC + 0x144 */
103  volatile u32 fcntrl; /* FEC + 0x148 */
104  volatile u32 r_bound; /* FEC + 0x14C */
105  volatile u32 r_fstart; /* FEC + 0x150 */
106  volatile u32 r_count; /* FEC + 0x154 */
107  volatile u32 r_lag; /* FEC + 0x158 */
108  volatile u32 r_read; /* FEC + 0x15C */
109  volatile u32 r_write; /* FEC + 0x160 */
110  volatile u32 x_count; /* FEC + 0x164 */
111  volatile u32 x_lag; /* FEC + 0x168 */
112  volatile u32 x_retry; /* FEC + 0x16C */
113  volatile u32 x_write; /* FEC + 0x170 */
114  volatile u32 x_read; /* FEC + 0x174 */
115 
116  volatile u32 reserved7[2]; /* FEC + 0x178-17C */
117  volatile u32 fm_cntrl; /* FEC + 0x180 */
118  volatile u32 rfifo_data; /* FEC + 0x184 */
119  volatile u32 rfifo_status; /* FEC + 0x188 */
120  volatile u32 rfifo_cntrl; /* FEC + 0x18C */
121  volatile u32 rfifo_lrf_ptr; /* FEC + 0x190 */
122  volatile u32 rfifo_lwf_ptr; /* FEC + 0x194 */
123  volatile u32 rfifo_alarm; /* FEC + 0x198 */
124  volatile u32 rfifo_rdptr; /* FEC + 0x19C */
125  volatile u32 rfifo_wrptr; /* FEC + 0x1A0 */
126  volatile u32 tfifo_data; /* FEC + 0x1A4 */
127  volatile u32 tfifo_status; /* FEC + 0x1A8 */
128  volatile u32 tfifo_cntrl; /* FEC + 0x1AC */
129  volatile u32 tfifo_lrf_ptr; /* FEC + 0x1B0 */
130  volatile u32 tfifo_lwf_ptr; /* FEC + 0x1B4 */
131  volatile u32 tfifo_alarm; /* FEC + 0x1B8 */
132  volatile u32 tfifo_rdptr; /* FEC + 0x1BC */
133  volatile u32 tfifo_wrptr; /* FEC + 0x1C0 */
134 
135  volatile u32 reset_cntrl; /* FEC + 0x1C4 */
136  volatile u32 xmit_fsm; /* FEC + 0x1C8 */
137 
138  volatile u32 reserved8[3]; /* FEC + 0x1CC-1D4 */
139  volatile u32 rdes_data0; /* FEC + 0x1D8 */
140  volatile u32 rdes_data1; /* FEC + 0x1DC */
141  volatile u32 r_length; /* FEC + 0x1E0 */
142  volatile u32 x_length; /* FEC + 0x1E4 */
143  volatile u32 x_addr; /* FEC + 0x1E8 */
144  volatile u32 cdes_data; /* FEC + 0x1EC */
145  volatile u32 status; /* FEC + 0x1F0 */
146  volatile u32 dma_control; /* FEC + 0x1F4 */
147  volatile u32 des_cmnd; /* FEC + 0x1F8 */
148  volatile u32 data; /* FEC + 0x1FC */
149 
150  volatile u32 rmon_t_drop; /* FEC + 0x200 */
151  volatile u32 rmon_t_packets; /* FEC + 0x204 */
152  volatile u32 rmon_t_bc_pkt; /* FEC + 0x208 */
153  volatile u32 rmon_t_mc_pkt; /* FEC + 0x20C */
154  volatile u32 rmon_t_crc_align; /* FEC + 0x210 */
155  volatile u32 rmon_t_undersize; /* FEC + 0x214 */
156  volatile u32 rmon_t_oversize; /* FEC + 0x218 */
157  volatile u32 rmon_t_frag; /* FEC + 0x21C */
158  volatile u32 rmon_t_jab; /* FEC + 0x220 */
159  volatile u32 rmon_t_col; /* FEC + 0x224 */
160  volatile u32 rmon_t_p64; /* FEC + 0x228 */
161  volatile u32 rmon_t_p65to127; /* FEC + 0x22C */
162  volatile u32 rmon_t_p128to255; /* FEC + 0x230 */
163  volatile u32 rmon_t_p256to511; /* FEC + 0x234 */
164  volatile u32 rmon_t_p512to1023; /* FEC + 0x238 */
165  volatile u32 rmon_t_p1024to2047; /* FEC + 0x23C */
166  volatile u32 rmon_t_p_gte2048; /* FEC + 0x240 */
167  volatile u32 rmon_t_octets; /* FEC + 0x244 */
168  volatile u32 ieee_t_drop; /* FEC + 0x248 */
169  volatile u32 ieee_t_frame_ok; /* FEC + 0x24C */
170  volatile u32 ieee_t_1col; /* FEC + 0x250 */
171  volatile u32 ieee_t_mcol; /* FEC + 0x254 */
172  volatile u32 ieee_t_def; /* FEC + 0x258 */
173  volatile u32 ieee_t_lcol; /* FEC + 0x25C */
174  volatile u32 ieee_t_excol; /* FEC + 0x260 */
175  volatile u32 ieee_t_macerr; /* FEC + 0x264 */
176  volatile u32 ieee_t_cserr; /* FEC + 0x268 */
177  volatile u32 ieee_t_sqe; /* FEC + 0x26C */
178  volatile u32 t_fdxfc; /* FEC + 0x270 */
179  volatile u32 ieee_t_octets_ok; /* FEC + 0x274 */
180 
181  volatile u32 reserved9[2]; /* FEC + 0x278-27C */
182  volatile u32 rmon_r_drop; /* FEC + 0x280 */
183  volatile u32 rmon_r_packets; /* FEC + 0x284 */
184  volatile u32 rmon_r_bc_pkt; /* FEC + 0x288 */
185  volatile u32 rmon_r_mc_pkt; /* FEC + 0x28C */
186  volatile u32 rmon_r_crc_align; /* FEC + 0x290 */
187  volatile u32 rmon_r_undersize; /* FEC + 0x294 */
188  volatile u32 rmon_r_oversize; /* FEC + 0x298 */
189  volatile u32 rmon_r_frag; /* FEC + 0x29C */
190  volatile u32 rmon_r_jab; /* FEC + 0x2A0 */
191 
192  volatile u32 rmon_r_resvd_0; /* FEC + 0x2A4 */
193 
194  volatile u32 rmon_r_p64; /* FEC + 0x2A8 */
195  volatile u32 rmon_r_p65to127; /* FEC + 0x2AC */
196  volatile u32 rmon_r_p128to255; /* FEC + 0x2B0 */
197  volatile u32 rmon_r_p256to511; /* FEC + 0x2B4 */
198  volatile u32 rmon_r_p512to1023; /* FEC + 0x2B8 */
199  volatile u32 rmon_r_p1024to2047; /* FEC + 0x2BC */
200  volatile u32 rmon_r_p_gte2048; /* FEC + 0x2C0 */
201  volatile u32 rmon_r_octets; /* FEC + 0x2C4 */
202  volatile u32 ieee_r_drop; /* FEC + 0x2C8 */
203  volatile u32 ieee_r_frame_ok; /* FEC + 0x2CC */
204  volatile u32 ieee_r_crc; /* FEC + 0x2D0 */
205  volatile u32 ieee_r_align; /* FEC + 0x2D4 */
206  volatile u32 r_macerr; /* FEC + 0x2D8 */
207  volatile u32 r_fdxfc; /* FEC + 0x2DC */
208  volatile u32 ieee_r_octets_ok; /* FEC + 0x2E0 */
209 
210  volatile u32 reserved10[6]; /* FEC + 0x2E4-2FC */
211 
212  volatile u32 reserved11[64]; /* FEC + 0x300-3FF */
213 };
214 
215 #define MPC5xxx_FEC_MIB_DISABLE 0x80000000
216 
217 #define MPC5xxx_FEC_IEVENT_HBERR 0x80000000
218 #define MPC5xxx_FEC_IEVENT_BABR 0x40000000
219 #define MPC5xxx_FEC_IEVENT_BABT 0x20000000
220 #define MPC5xxx_FEC_IEVENT_GRA 0x10000000
221 #define MPC5xxx_FEC_IEVENT_TFINT 0x08000000
222 #define MPC5xxx_FEC_IEVENT_MII 0x00800000
223 #define MPC5xxx_FEC_IEVENT_LATE_COL 0x00200000
224 #define MPC5xxx_FEC_IEVENT_COL_RETRY_LIM 0x00100000
225 #define MPC5xxx_FEC_IEVENT_XFIFO_UN 0x00080000
226 #define MPC5xxx_FEC_IEVENT_XFIFO_ERROR 0x00040000
227 #define MPC5xxx_FEC_IEVENT_RFIFO_ERROR 0x00020000
228 
229 #define MPC5xxx_FEC_IMASK_HBERR 0x80000000
230 #define MPC5xxx_FEC_IMASK_BABR 0x40000000
231 #define MPC5xxx_FEC_IMASK_BABT 0x20000000
232 #define MPC5xxx_FEC_IMASK_GRA 0x10000000
233 #define MPC5xxx_FEC_IMASK_MII 0x00800000
234 #define MPC5xxx_FEC_IMASK_LATE_COL 0x00200000
235 #define MPC5xxx_FEC_IMASK_COL_RETRY_LIM 0x00100000
236 #define MPC5xxx_FEC_IMASK_XFIFO_UN 0x00080000
237 #define MPC5xxx_FEC_IMASK_XFIFO_ERROR 0x00040000
238 #define MPC5xxx_FEC_IMASK_RFIFO_ERROR 0x00020000
239 
240 #define MPC5xxx_FEC_RCNTRL_MAX_FL_SHIFT 16
241 #define MPC5xxx_FEC_RCNTRL_LOOP 0x01
242 #define MPC5xxx_FEC_RCNTRL_DRT 0x02
243 #define MPC5xxx_FEC_RCNTRL_MII_MODE 0x04
244 #define MPC5xxx_FEC_RCNTRL_PROM 0x08
245 #define MPC5xxx_FEC_RCNTRL_BC_REJ 0x10
246 #define MPC5xxx_FEC_RCNTRL_FCE 0x20
247 
248 #define MPC5xxx_FEC_TCNTRL_GTS 0x00000001
249 #define MPC5xxx_FEC_TCNTRL_HBC 0x00000002
250 #define MPC5xxx_FEC_TCNTRL_FDEN 0x00000004
251 #define MPC5xxx_FEC_TCNTRL_TFC_PAUSE 0x00000008
252 #define MPC5xxx_FEC_TCNTRL_RFC_PAUSE 0x00000010
253 
254 #define MPC5xxx_FEC_ECNTRL_RESET 0x00000001
255 #define MPC5xxx_FEC_ECNTRL_ETHER_EN 0x00000002
256 
257 #define MPC5xxx_FEC_RESET_DELAY 50 /* uS */
258 
259 
260 /* Receive & Transmit Buffer Descriptor definitions */
261 struct mpc5xxx_fec_bd {
262  volatile u32 status;
263  volatile u32 data;
264 };
265 
266 /* Receive data buffer format */
267 struct mpc5xxx_rbuf {
268  u8 data[MPC5xxx_FEC_RECV_BUFFER_SIZE_BC];
269 };
270 
271 struct fec_queue {
272  volatile struct mpc5xxx_fec_bd *bd_base;
273  struct rtskb **skb_base;
274  u16 last_index;
275  u16 start_index;
276  u16 finish_index;
277 };
278 
279 #ifdef CONFIG_XENO_DRIVERS_NET_USE_MDIO
280 #define MII_ADVERTISE_HALF (ADVERTISE_100HALF | ADVERTISE_10HALF | \
281  ADVERTISE_CSMA)
282 
283 #define MII_ADVERTISE_ALL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
284  MII_ADVERTISE_HALF)
285 #ifdef PHY_INTERRUPT
286 #define MII_ADVERTISE_DEFAULT MII_ADVERTISE_ALL
287 #else
288 #define MII_ADVERTISE_DEFAULT MII_ADVERTISE_HALF
289 #endif
290 
291 typedef struct {
292  uint mii_data;
293  void (*funct)(uint mii_reg, struct rtnet_device *dev, uint data);
294 } phy_cmd_t;
295 
296 typedef struct {
297  uint id;
298  char *name;
299 
300  const phy_cmd_t *config;
301  const phy_cmd_t *startup;
302  const phy_cmd_t *ack_int;
303  const phy_cmd_t *shutdown;
304 } phy_info_t;
305 #endif /* CONFIG_XENO_DRIVERS_NET_USE_MDIO */
306 
307 struct mpc5xxx_fec_priv {
308  int full_duplex;
309  int tx_full;
310  int r_tasknum;
311  int t_tasknum;
312  int r_irq;
313  int t_irq;
314  rtdm_irq_t irq_handle;
315  rtdm_irq_t r_irq_handle;
316  rtdm_irq_t t_irq_handle;
317  u32 last_transmit_time;
318  u32 last_receive_time;
319  struct mpc5xxx_fec *fec;
320  struct mpc5xxx_sram_fec *sram;
321  struct mpc5xxx_gpio *gpio;
322  struct mpc5xxx_sdma *sdma;
323  struct fec_queue r_queue;
324  struct rtskb *rskb[MPC5xxx_FEC_RBD_NUM];
325  struct fec_queue t_queue;
326  struct rtskb *tskb[MPC5xxx_FEC_TBD_NUM];
327  rtdm_lock_t lock;
328  unsigned long open_time;
329  struct net_device_stats stats;
330 #ifdef CONFIG_XENO_DRIVERS_NET_USE_MDIO
331  uint phy_id;
332  uint phy_id_done;
333  uint phy_status;
334  uint phy_speed;
335  phy_info_t *phy;
336  struct tq_struct phy_task;
337  volatile uint sequence_done;
338  uint link;
339  uint phy_addr;
340 
341  struct tq_struct link_up_task;
342  int duplex_change;
343  int link_up;
344 
345  struct timer_list phy_timer_list;
346  u16 old_status;
347 #endif /* CONFIG_XENO_DRIVERS_NET_USE_MDIO */
348 };
349 
350 struct mpc5xxx_sram_fec {
351  volatile struct mpc5xxx_fec_bd tbd[MPC5xxx_FEC_TBD_NUM];
352  volatile struct mpc5xxx_fec_bd rbd[MPC5xxx_FEC_RBD_NUM];
353 };
354 
355 #define MPC5xxx_FEC_RBD_READY 0x40000000
356 #define MPC5xxx_FEC_RBD_RFD 0x08000000 /* receive frame done */
357 
358 #define MPC5xxx_FEC_RBD_INIT MPC5xxx_FEC_RBD_READY
359 
360 #define MPC5xxx_FEC_TBD_READY 0x40000000
361 #define MPC5xxx_FEC_TBD_TFD 0x08000000 /* transmit frame done */
362 #define MPC5xxx_FEC_TBD_INT 0x04000000 /* Interrupt */
363 
364 #define MPC5xxx_FEC_TBD_INIT (MPC5xxx_FEC_TBD_INT | MPC5xxx_FEC_TBD_TFD | \
365  MPC5xxx_FEC_TBD_READY)
366 
367 
368 
369 /* MII-related definitions */
370 #define MPC5xxx_FEC_MII_DATA_ST 0x40000000 /* Start frame */
371 #define MPC5xxx_FEC_MII_DATA_OP_RD 0x20000000 /* Perform read */
372 #define MPC5xxx_FEC_MII_DATA_OP_WR 0x10000000 /* Perform write */
373 #define MPC5xxx_FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address mask */
374 #define MPC5xxx_FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register mask */
375 #define MPC5xxx_FEC_MII_DATA_TA 0x00020000 /* Turnaround */
376 #define MPC5xxx_FEC_MII_DATA_DATAMSK 0x00000fff /* PHY data mask */
377 
378 #define MPC5xxx_FEC_MII_DATA_RA_SHIFT 0x12 /* MII reg addr bits */
379 #define MPC5xxx_FEC_MII_DATA_PA_SHIFT 0x17 /* MII PHY addr bits */
380 
381 #define MPC5xxx_FEC_MII_SPEED (5 * 2)
382 
383 const char mpc5xxx_fec_name[] = "eth0";
384 
385 struct mibCounters {
386  unsigned int byteReceived;
387  unsigned int byteSent;
388  unsigned int framesReceived;
389  unsigned int framesSent;
390  unsigned int totalByteReceived;
391  unsigned int totalFramesReceived;
392  unsigned int broadcastFramesReceived;
393  unsigned int multicastFramesReceived;
394  unsigned int cRCError;
395  unsigned int oversizeFrames;
396  unsigned int fragments;
397  unsigned int jabber;
398  unsigned int collision;
399  unsigned int lateCollision;
400  unsigned int frames64;
401  unsigned int frames65_127;
402  unsigned int frames128_255;
403  unsigned int frames256_511;
404  unsigned int frames512_1023;
405  unsigned int frames1024_MaxSize;
406  unsigned int macRxError;
407  unsigned int droppedFrames;
408  unsigned int outMulticastFrames;
409  unsigned int outBroadcastFrames;
410  unsigned int undersizeFrames;
411 };
412 
413 #define MPC5xxx_FEC_WATCHDOG_TIMEOUT ((400*HZ)/1000)
414 
415 
416 #define MPC5xxx_FEC_FRAME_LAST 0x08000000 /* Last */
417 #define MPC5xxx_FEC_FRAME_M 0x01000000 /* M? */
418 #define MPC5xxx_FEC_FRAME_BC 0x00800000 /* Broadcast */
419 #define MPC5xxx_FEC_FRAME_MC 0x00400000 /* Multicast */
420 #define MPC5xxx_FEC_FRAME_LG 0x00200000 /* Length error */
421 #define MPC5xxx_FEC_FRAME_NO 0x00100000 /* Non-octet aligned frame error */
422 #define MPC5xxx_FEC_FRAME_CR 0x00040000 /* CRC frame error */
423 #define MPC5xxx_FEC_FRAME_OV 0x00020000 /* Overrun error */
424 #define MPC5xxx_FEC_FRAME_TR 0x00010000 /* Truncated error */
425 
426 
427 
428 #endif /* __RT_MPC52XX_FEC_H_ */
ipipe_spinlock_t rtdm_lock_t
Lock variable.
Definition: driver.h:551