Xenomai  3.0.8
rt_smc91111.h
1 /*------------------------------------------------------------------------
2  . smc91111.h - macros for the LAN91C111 Ethernet Driver
3  .
4  . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
5  . Developed by Simple Network Magic Corporation (SNMC)
6  . Copyright (C) 1996 by Erik Stahlman (ES)
7  .
8  . This program is free software; you can redistribute it and/or modify
9  . it under the terms of the GNU General Public License as published by
10  . the Free Software Foundation; either version 2 of the License, or
11  . (at your option) any later version.
12  .
13  . This program is distributed in the hope that it will be useful,
14  . but WITHOUT ANY WARRANTY; without even the implied warranty of
15  . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  . GNU General Public License for more details.
17  .
18  . You should have received a copy of the GNU General Public License
19  . along with this program; if not, write to the Free Software
20  . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  .
22  . This file contains register information and access macros for
23  . the LAN91C111 single chip ethernet controller. It is a modified
24  . version of the smc9194.h file.
25  .
26  . Information contained in this file was obtained from the LAN91C111
27  . manual from SMC. To get a copy, if you really want one, you can find
28  . information under www.smsc.com.
29  .
30  . Authors
31  . Erik Stahlman ( erik@vt.edu )
32  . Daris A Nevil ( dnevil@snmc.com )
33  .
34  . History
35  . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device
36  .
37  ---------------------------------------------------------------------------*/
38 #ifndef _SMC91111_H_
39 #define _SMC91111_H_
40 
41 /* I want some simple types */
42 
43 typedef unsigned char byte;
44 typedef unsigned short word;
45 typedef unsigned long int dword;
46 
47 
48 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
49 
50 #define SMC_IO_EXTENT 16
51 
52 
53 /*---------------------------------------------------------------
54  .
55  . A description of the SMSC registers is probably in order here,
56  . although for details, the SMC datasheet is invaluable.
57  .
58  . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
59  . are accessed by writing a number into the BANK_SELECT register
60  . ( I also use a SMC_SELECT_BANK macro for this ).
61  .
62  . The banks are configured so that for most purposes, bank 2 is all
63  . that is needed for simple run time tasks.
64  -----------------------------------------------------------------------*/
65 
66 /*
67  . Bank Select Register:
68  .
69  . yyyy yyyy 0000 00xx
70  . xx = bank number
71  . yyyy yyyy = 0x33, for identification purposes.
72 */
73 #define BANK_SELECT 14
74 
75 // Transmit Control Register
76 /* BANK 0 */
77 #define TCR_REG 0x0000 // transmit control register
78 #define TCR_ENABLE 0x0001 // When 1 we can transmit
79 #define TCR_LOOP 0x0002 // Controls output pin LBK
80 #define TCR_FORCOL 0x0004 // When 1 will force a collision
81 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
82 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
83 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
84 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
85 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
86 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
87 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
88 
89 #define TCR_CLEAR 0 /* do NOTHING */
90 /* the default settings for the TCR register : */
91 /* QUESTION: do I want to enable padding of short packets ? */
92 #define TCR_DEFAULT TCR_ENABLE
93 
94 
95 // EPH Status Register
96 /* BANK 0 */
97 #define EPH_STATUS_REG 0x0002
98 #define ES_TX_SUC 0x0001 // Last TX was successful
99 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
100 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
101 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
102 #define ES_16COL 0x0010 // 16 Collisions Reached
103 #define ES_SQET 0x0020 // Signal Quality Error Test
104 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
105 #define ES_TXDEFR 0x0080 // Transmit Deferred
106 #define ES_LATCOL 0x0200 // Late collision detected on last tx
107 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
108 #define ES_EXC_DEF 0x0800 // Excessive Deferral
109 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
110 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
111 #define ES_TXUNRN 0x8000 // Tx Underrun
112 
113 
114 // Receive Control Register
115 /* BANK 0 */
116 #define RCR_REG 0x0004
117 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
118 #define RCR_PRMS 0x0002 // Enable promiscuous mode
119 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
120 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
121 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
122 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
123 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
124 #define RCR_SOFTRST 0x8000 // resets the chip
125 
126 /* the normal settings for the RCR register : */
127 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
128 #define RCR_CLEAR 0x0 // set it to a base state
129 
130 // Counter Register
131 /* BANK 0 */
132 #define COUNTER_REG 0x0006
133 
134 // Memory Information Register
135 /* BANK 0 */
136 #define MIR_REG 0x0008
137 
138 // Receive/Phy Control Register
139 /* BANK 0 */
140 #define RPC_REG 0x000A
141 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
142 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
143 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
144 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
145 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
146 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
147 #define RPC_LED_RES (0x01) // LED = Reserved
148 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
149 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
150 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
151 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
152 #define RPC_LED_TX (0x06) // LED = TX packet occurred
153 #define RPC_LED_RX (0x07) // LED = RX packet occurred
154 #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
155 
156 /* Bank 0 0x000C is reserved */
157 
158 // Bank Select Register
159 /* All Banks */
160 #define BSR_REG 0x000E
161 
162 
163 // Configuration Reg
164 /* BANK 1 */
165 #define CONFIG_REG 0x0000
166 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
167 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
168 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
169 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
170 
171 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
172 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
173 
174 
175 // Base Address Register
176 /* BANK 1 */
177 #define BASE_REG 0x0002
178 
179 
180 // Individual Address Registers
181 /* BANK 1 */
182 #define ADDR0_REG 0x0004
183 #define ADDR1_REG 0x0006
184 #define ADDR2_REG 0x0008
185 
186 
187 // General Purpose Register
188 /* BANK 1 */
189 #define GP_REG 0x000A
190 
191 
192 // Control Register
193 /* BANK 1 */
194 #define CTL_REG 0x000C
195 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
196 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
197 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
198 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
199 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
200 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
201 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
202 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
203 
204 
205 // MMU Command Register
206 /* BANK 2 */
207 #define MMU_CMD_REG 0x0000
208 #define MC_BUSY 1 // When 1 the last release has not completed
209 #define MC_NOP (0<<5) // No Op
210 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
211 #define MC_RESET (2<<5) // Reset MMU to initial state
212 #define MC_REMOVE (3<<5) // Remove the current rx packet
213 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
214 #define MC_FREEPKT (5<<5) // Release packet in PNR register
215 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
216 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
217 
218 
219 // Packet Number Register
220 /* BANK 2 */
221 #define PN_REG 0x0002
222 
223 
224 // Allocation Result Register
225 /* BANK 2 */
226 #define AR_REG 0x0003
227 #define AR_FAILED 0x80 // Alocation Failed
228 
229 
230 // RX FIFO Ports Register
231 /* BANK 2 */
232 #define RXFIFO_REG 0x0004 // Must be read as a word
233 #define RXFIFO_REMPTY 0x8000 // RX FIFO Empty
234 
235 
236 // TX FIFO Ports Register
237 /* BANK 2 */
238 #define TXFIFO_REG RXFIFO_REG // Must be read as a word
239 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
240 
241 
242 // Pointer Register
243 /* BANK 2 */
244 #define PTR_REG 0x0006
245 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
246 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
247 #define PTR_READ 0x2000 // When 1 the operation is a read
248 
249 
250 // Data Register
251 /* BANK 2 */
252 #define DATA_REG 0x0008
253 
254 
255 // Interrupt Status/Acknowledge Register
256 /* BANK 2 */
257 #define INT_REG 0x000C
258 
259 
260 // Interrupt Mask Register
261 /* BANK 2 */
262 #define IM_REG 0x000D
263 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
264 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
265 #define IM_EPH_INT 0x20 // Set by Etheret Protocol Handler section
266 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
267 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
268 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
269 #define IM_TX_INT 0x02 // Transmit Interrrupt
270 #define IM_RCV_INT 0x01 // Receive Interrupt
271 
272 
273 // Multicast Table Registers
274 /* BANK 3 */
275 #define MCAST_REG1 0x0000
276 #define MCAST_REG2 0x0002
277 #define MCAST_REG3 0x0004
278 #define MCAST_REG4 0x0006
279 
280 
281 // Management Interface Register (MII)
282 /* BANK 3 */
283 #define MII_REG 0x0008
284 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
285 #define MII_MDOE 0x0008 // MII Output Enable
286 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
287 #define MII_MDI 0x0002 // MII Input, pin MDI
288 #define MII_MDO 0x0001 // MII Output, pin MDO
289 
290 
291 // Revision Register
292 /* BANK 3 */
293 #define REV_REG 0x000A /* ( hi: chip id low: rev # ) */
294 
295 
296 // Early RCV Register
297 /* BANK 3 */
298 /* this is NOT on SMC9192 */
299 #define ERCV_REG 0x000C
300 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
301 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
302 
303 // External Register
304 /* BANK 7 */
305 #define EXT_REG 0x0000
306 
307 
308 #define CHIP_9192 3
309 #define CHIP_9194 4
310 #define CHIP_9195 5
311 #define CHIP_9196 6
312 #define CHIP_91100 7
313 #define CHIP_91100FD 8
314 #define CHIP_91111FD 9
315 
316 static const char * chip_ids[ 15 ] = {
317  NULL, NULL, NULL,
318  /* 3 */ "SMC91C90/91C92",
319  /* 4 */ "SMC91C94",
320  /* 5 */ "SMC91C95",
321  /* 6 */ "SMC91C96",
322  /* 7 */ "SMC91C100",
323  /* 8 */ "SMC91C100FD",
324  /* 9 */ "SMC91C11xFD",
325  NULL, NULL,
326  NULL, NULL, NULL};
327 
328 /*
329  . Transmit status bits
330 */
331 #define TS_SUCCESS 0x0001
332 #define TS_LOSTCAR 0x0400
333 #define TS_LATCOL 0x0200
334 #define TS_16COL 0x0010
335 
336 /*
337  . Receive status bits
338 */
339 #define RS_ALGNERR 0x8000
340 #define RS_BRODCAST 0x4000
341 #define RS_BADCRC 0x2000
342 #define RS_ODDFRAME 0x1000 // bug: the LAN91C111 never sets this on receive
343 #define RS_TOOLONG 0x0800
344 #define RS_TOOSHORT 0x0400
345 #define RS_MULTICAST 0x0001
346 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
347 
348 
349 // PHY Types
350 enum {
351  PHY_LAN83C183 = 1, // LAN91C111 Internal PHY
352  PHY_LAN83C180
353 };
354 
355 
356 // PHY Register Addresses (LAN91C111 Internal PHY)
357 
358 // PHY Control Register
359 #define PHY_CNTL_REG 0x00
360 #define PHY_CNTL_RST 0x8000 // 1=PHY Reset
361 #define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback
362 #define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs
363 #define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation
364 #define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode
365 #define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled
366 #define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate
367 #define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex
368 #define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test
369 
370 // PHY Status Register
371 #define PHY_STAT_REG 0x01
372 #define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable
373 #define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable
374 #define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable
375 #define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable
376 #define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable
377 #define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble
378 #define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed
379 #define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected
380 #define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable
381 #define PHY_STAT_LINK 0x0004 // 1=valid link
382 #define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition
383 #define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented
384 
385 // PHY Identifier Registers
386 #define PHY_ID1_REG 0x02 // PHY Identifier 1
387 #define PHY_ID2_REG 0x03 // PHY Identifier 2
388 
389 // PHY Auto-Negotiation Advertisement Register
390 #define PHY_AD_REG 0x04
391 #define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page
392 #define PHY_AD_ACK 0x4000 // 1=got link code word from remote
393 #define PHY_AD_RF 0x2000 // 1=advertise remote fault
394 #define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4
395 #define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX
396 #define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX
397 #define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX
398 #define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX
399 #define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA
400 
401 // PHY Auto-negotiation Remote End Capability Register
402 #define PHY_RMT_REG 0x05
403 // Uses same bit definitions as PHY_AD_REG
404 
405 // PHY Configuration Register 1
406 #define PHY_CFG1_REG 0x10
407 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
408 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
409 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
410 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
411 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
412 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
413 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
414 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
415 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
416 #define PHY_CFG1_TLVL_MASK 0x003C
417 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
418 
419 
420 // PHY Configuration Register 2
421 #define PHY_CFG2_REG 0x11
422 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
423 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
424 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
425 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
426 
427 // PHY Status Output (and Interrupt status) Register
428 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
429 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
430 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
431 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
432 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
433 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
434 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
435 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
436 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
437 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
438 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
439 
440 // PHY Interrupt/Status Mask Register
441 #define PHY_MASK_REG 0x13 // Interrupt Mask
442 // Uses the same bit definitions as PHY_INT_REG
443 
444 
445 
446 /*-------------------------------------------------------------------------
447  . I define some macros to make it easier to do somewhat common
448  . or slightly complicated, repeated tasks.
449  --------------------------------------------------------------------------*/
450 
451 /* select a register bank, 0 to 3 */
452 
453 #define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); }
454 
455 /* this enables an interrupt in the interrupt mask register */
456 #define SMC_ENABLE_INT(x) {\
457  unsigned char mask;\
458  SMC_SELECT_BANK(2);\
459  mask = inb( ioaddr + IM_REG );\
460  mask |= (x);\
461  outb( mask, ioaddr + IM_REG ); \
462 }
463 
464 /* this disables an interrupt from the interrupt mask register */
465 
466 #define SMC_DISABLE_INT(x) {\
467  unsigned char mask;\
468  SMC_SELECT_BANK(2);\
469  mask = inb( ioaddr + IM_REG );\
470  mask &= ~(x);\
471  outb( mask, ioaddr + IM_REG ); \
472 }
473 
474 /*----------------------------------------------------------------------
475  . Define the interrupts that I want to receive from the card
476  .
477  . I want:
478  . IM_EPH_INT, for nasty errors
479  . IM_RCV_INT, for happy received packets
480  . IM_RX_OVRN_INT, because I have to kick the receiver
481  . IM_MDINT, for PHY Register 18 Status Changes
482  --------------------------------------------------------------------------*/
483 #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
484  IM_MDINT)
485 
486 
487 #ifdef CONFIG_SYSCTL
488 
489 
490 /*
491  * Declarations for the sysctl interface, which allows users the ability to
492  * control the finer aspects of the LAN91C111 chip. Since the smc
493  * module currently registers its sysctl table dynamically, the sysctl path
494  * for module FOO is /proc/sys/dev/ethX/FOO
495  */
496 #define CTL_SMC (CTL_BUS+1389) // arbitrary and hopefully unused
497 
498 enum {
499  CTL_SMC_INFO = 1, // Sysctl files information
500  CTL_SMC_SWVER, // Driver Software Version Info
501  CTL_SMC_SWFDUP, // Switched Full Duplex Mode
502  CTL_SMC_EPHLOOP, // EPH Block Internal Loopback
503  CTL_SMC_MIIOP, // MII Operation
504  CTL_SMC_AUTONEG, // Auto-negotiate Mode
505  CTL_SMC_RFDUPLX, // Request Full Duplex Mode
506  CTL_SMC_RSPEED, // Request Speed Selection
507  CTL_SMC_AFDUPLX, // Actual Full Duplex Mode
508  CTL_SMC_ASPEED, // Actual Speed Selection
509  CTL_SMC_LNKFAIL, // Link Failed
510  CTL_SMC_FORCOL, // Force a Collision
511  CTL_SMC_FILTCAR, // Filter Carrier
512  CTL_SMC_FREEMEM, // Free Buffer Memory
513  CTL_SMC_TOTMEM, // Total Buffer Memory
514  CTL_SMC_LEDA, // Output of LED-A
515  CTL_SMC_LEDB, // Output of LED-B
516  CTL_SMC_CHIPREV, // LAN91C111 Chip Revision ID
517 #ifdef SMC_DEBUG
518  // Register access for debugging
519  CTL_SMC_REG_BSR, // Bank Select
520  CTL_SMC_REG_TCR, // Transmit Control
521  CTL_SMC_REG_ESR, // EPH Status
522  CTL_SMC_REG_RCR, // Receive Control
523  CTL_SMC_REG_CTRR, // Counter
524  CTL_SMC_REG_MIR, // Memory Information
525  CTL_SMC_REG_RPCR, // Receive/Phy Control
526  CTL_SMC_REG_CFGR, // Configuration
527  CTL_SMC_REG_BAR, // Base Address
528  CTL_SMC_REG_IAR0, // Individual Address 0
529  CTL_SMC_REG_IAR1, // Individual Address 1
530  CTL_SMC_REG_IAR2, // Individual Address 2
531  CTL_SMC_REG_GPR, // General Purpose
532  CTL_SMC_REG_CTLR, // Control
533  CTL_SMC_REG_MCR, // MMU Command
534  CTL_SMC_REG_PNR, // Packet Number
535  CTL_SMC_REG_FPR, // FIFO Ports
536  CTL_SMC_REG_PTR, // Pointer
537  CTL_SMC_REG_DR, // Data
538  CTL_SMC_REG_ISR, // Interrupt Status
539  CTL_SMC_REG_MTR1, // Multicast Table Entry 1
540  CTL_SMC_REG_MTR2, // Multicast Table Entry 2
541  CTL_SMC_REG_MTR3, // Multicast Table Entry 3
542  CTL_SMC_REG_MTR4, // Multicast Table Entry 4
543  CTL_SMC_REG_MIIR, // Management Interface
544  CTL_SMC_REG_REVR, // Revision
545  CTL_SMC_REG_ERCVR, // Early RCV
546  CTL_SMC_REG_EXTR, // External
547  CTL_SMC_PHY_CTRL, // PHY Control
548  CTL_SMC_PHY_STAT, // PHY Status
549  CTL_SMC_PHY_ID1, // PHY ID1
550  CTL_SMC_PHY_ID2, // PHY ID2
551  CTL_SMC_PHY_ADC, // PHY Advertise Capability
552  CTL_SMC_PHY_REMC, // PHY Advertise Capability
553  CTL_SMC_PHY_CFG1, // PHY Configuration 1
554  CTL_SMC_PHY_CFG2, // PHY Configuration 2
555  CTL_SMC_PHY_INT, // PHY Interrupt/Status Output
556  CTL_SMC_PHY_MASK, // PHY Interrupt/Status Mask
557 #endif
558  // ---------------------------------------------------
559  CTL_SMC_LAST_ENTRY // Add new entries above the line
560 };
561 
562 #endif // CONFIG_SYSCTL
563 
564 #endif /* _SMC_91111_H_ */
565 
566