Xenomai  3.0.8
rtcan_mscan_regs.h
1 /*
2  * Copyright (C) 2006 Wolfgang Grandegger <wg@grandegger.com>
3  *
4  * Based on linux-2.4.25/include/asm-ppc/mpc5xxx.h
5  * Prototypes, etc. for the Motorola MPC5xxx embedded cpu chips
6  *
7  * Author: Dale Farnsworth <dfarnsworth@mvista.com>
8  *
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful, but
16  * WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18  * General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software Foundation,
22  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23  */
24 
25 #ifndef __RTCAN_MSCAN_REGS_H_
26 #define __RTCAN_MSCAN_REGS_H_
27 
28 #include <linux/version.h>
29 #include <linux/of_platform.h>
30 #include <asm/mpc52xx.h>
31 
32 static inline void __iomem *mpc5xxx_gpio_find_and_map(void)
33 {
34  struct device_node *ofn;
35  ofn = of_find_compatible_node(NULL, NULL, "mpc5200-gpio");
36  if (!ofn)
37  ofn = of_find_compatible_node(NULL, NULL, "fsl,mpc5200-gpio");
38  return ofn ? of_iomap(ofn, 0) : NULL;
39 }
40 
41 #define MPC5xxx_GPIO mpc5xxx_gpio_find_and_map()
42 #define mpc5xxx_gpio mpc52xx_gpio
43 
44 #define mpc5xxx_get_of_node(ofdev) (ofdev)->dev.of_node
45 
46 #define MSCAN_CAN1_ADDR (MSCAN_MBAR + 0x0900) /* MSCAN Module 1 */
47 #define MSCAN_CAN2_ADDR (MSCAN_MBAR + 0x0980) /* MSCAN Module 2 */
48 #define MSCAN_SIZE 0x80
49 
50 /* MSCAN control register 0 (CANCTL0) bits */
51 #define MSCAN_RXFRM 0x80
52 #define MSCAN_RXACT 0x40
53 #define MSCAN_CSWAI 0x20
54 #define MSCAN_SYNCH 0x10
55 #define MSCAN_TIME 0x08
56 #define MSCAN_WUPE 0x04
57 #define MSCAN_SLPRQ 0x02
58 #define MSCAN_INITRQ 0x01
59 
60 /* MSCAN control register 1 (CANCTL1) bits */
61 #define MSCAN_CANE 0x80
62 #define MSCAN_CLKSRC 0x40
63 #define MSCAN_LOOPB 0x20
64 #define MSCAN_LISTEN 0x10
65 #define MSCAN_WUPM 0x04
66 #define MSCAN_SLPAK 0x02
67 #define MSCAN_INITAK 0x01
68 
69 /* MSCAN receiver flag register (CANRFLG) bits */
70 #define MSCAN_WUPIF 0x80
71 #define MSCAN_CSCIF 0x40
72 #define MSCAN_RSTAT1 0x20
73 #define MSCAN_RSTAT0 0x10
74 #define MSCAN_TSTAT1 0x08
75 #define MSCAN_TSTAT0 0x04
76 #define MSCAN_OVRIF 0x02
77 #define MSCAN_RXF 0x01
78 
79 /* MSCAN receiver interrupt enable register (CANRIER) bits */
80 #define MSCAN_WUPIE 0x80
81 #define MSCAN_CSCIE 0x40
82 #define MSCAN_RSTATE1 0x20
83 #define MSCAN_RSTATE0 0x10
84 #define MSCAN_TSTATE1 0x08
85 #define MSCAN_TSTATE0 0x04
86 #define MSCAN_OVRIE 0x02
87 #define MSCAN_RXFIE 0x01
88 
89 /* MSCAN transmitter flag register (CANTFLG) bits */
90 #define MSCAN_TXE2 0x04
91 #define MSCAN_TXE1 0x02
92 #define MSCAN_TXE0 0x01
93 #define MSCAN_TXE (MSCAN_TXE2 | MSCAN_TXE1 | MSCAN_TXE0)
94 
95 /* MSCAN transmitter interrupt enable register (CANTIER) bits */
96 #define MSCAN_TXIE2 0x04
97 #define MSCAN_TXIE1 0x02
98 #define MSCAN_TXIE0 0x01
99 #define MSCAN_TXIE (MSCAN_TXIE2 | MSCAN_TXIE1 | MSCAN_TXIE0)
100 
101 /* MSCAN transmitter message abort request (CANTARQ) bits */
102 #define MSCAN_ABTRQ2 0x04
103 #define MSCAN_ABTRQ1 0x02
104 #define MSCAN_ABTRQ0 0x01
105 
106 /* MSCAN transmitter message abort ack (CANTAAK) bits */
107 #define MSCAN_ABTAK2 0x04
108 #define MSCAN_ABTAK1 0x02
109 #define MSCAN_ABTAK0 0x01
110 
111 /* MSCAN transmit buffer selection (CANTBSEL) bits */
112 #define MSCAN_TX2 0x04
113 #define MSCAN_TX1 0x02
114 #define MSCAN_TX0 0x01
115 
116 /* MSCAN ID acceptance control register (CANIDAC) bits */
117 #define MSCAN_IDAM1 0x20
118 #define MSCAN_IDAM0 0x10
119 #define MSCAN_IDHIT2 0x04
120 #define MSCAN_IDHIT1 0x02
121 #define MSCAN_IDHIT0 0x01
122 
123 struct mscan_msgbuf {
124  volatile u8 idr[0x8]; /* 0x00 */
125  volatile u8 dsr[0x10]; /* 0x08 */
126  volatile u8 dlr; /* 0x18 */
127  volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */
128  volatile u16 rsrv1; /* 0x1A */
129  volatile u8 tsrh; /* 0x1C */
130  volatile u8 tsrl; /* 0x1D */
131  volatile u16 rsrv2; /* 0x1E */
132 };
133 
134 struct mscan_regs {
135  volatile u8 canctl0; /* MSCAN + 0x00 */
136  volatile u8 canctl1; /* MSCAN + 0x01 */
137  volatile u16 rsrv1; /* MSCAN + 0x02 */
138  volatile u8 canbtr0; /* MSCAN + 0x04 */
139  volatile u8 canbtr1; /* MSCAN + 0x05 */
140  volatile u16 rsrv2; /* MSCAN + 0x06 */
141  volatile u8 canrflg; /* MSCAN + 0x08 */
142  volatile u8 canrier; /* MSCAN + 0x09 */
143  volatile u16 rsrv3; /* MSCAN + 0x0A */
144  volatile u8 cantflg; /* MSCAN + 0x0C */
145  volatile u8 cantier; /* MSCAN + 0x0D */
146  volatile u16 rsrv4; /* MSCAN + 0x0E */
147  volatile u8 cantarq; /* MSCAN + 0x10 */
148  volatile u8 cantaak; /* MSCAN + 0x11 */
149  volatile u16 rsrv5; /* MSCAN + 0x12 */
150  volatile u8 cantbsel; /* MSCAN + 0x14 */
151  volatile u8 canidac; /* MSCAN + 0x15 */
152  volatile u16 rsrv6[3]; /* MSCAN + 0x16 */
153  volatile u8 canrxerr; /* MSCAN + 0x1C */
154  volatile u8 cantxerr; /* MSCAN + 0x1D */
155  volatile u16 rsrv7; /* MSCAN + 0x1E */
156  volatile u8 canidar0; /* MSCAN + 0x20 */
157  volatile u8 canidar1; /* MSCAN + 0x21 */
158  volatile u16 rsrv8; /* MSCAN + 0x22 */
159  volatile u8 canidar2; /* MSCAN + 0x24 */
160  volatile u8 canidar3; /* MSCAN + 0x25 */
161  volatile u16 rsrv9; /* MSCAN + 0x26 */
162  volatile u8 canidmr0; /* MSCAN + 0x28 */
163  volatile u8 canidmr1; /* MSCAN + 0x29 */
164  volatile u16 rsrv10; /* MSCAN + 0x2A */
165  volatile u8 canidmr2; /* MSCAN + 0x2C */
166  volatile u8 canidmr3; /* MSCAN + 0x2D */
167  volatile u16 rsrv11; /* MSCAN + 0x2E */
168  volatile u8 canidar4; /* MSCAN + 0x30 */
169  volatile u8 canidar5; /* MSCAN + 0x31 */
170  volatile u16 rsrv12; /* MSCAN + 0x32 */
171  volatile u8 canidar6; /* MSCAN + 0x34 */
172  volatile u8 canidar7; /* MSCAN + 0x35 */
173  volatile u16 rsrv13; /* MSCAN + 0x36 */
174  volatile u8 canidmr4; /* MSCAN + 0x38 */
175  volatile u8 canidmr5; /* MSCAN + 0x39 */
176  volatile u16 rsrv14; /* MSCAN + 0x3A */
177  volatile u8 canidmr6; /* MSCAN + 0x3C */
178  volatile u8 canidmr7; /* MSCAN + 0x3D */
179  volatile u16 rsrv15; /* MSCAN + 0x3E */
180 
181  struct mscan_msgbuf canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */
182  struct mscan_msgbuf cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */
183 };
184 
185 /* Clock source selection
186  */
187 #define MSCAN_CLKSRC_BUS 0
188 #define MSCAN_CLKSRC_XTAL MSCAN_CLKSRC
189 #define MSCAN_CLKSRC_IPS MSCAN_CLKSRC
190 
191 /* Message type access macros.
192  */
193 #define MSCAN_BUF_STD_RTR 0x10
194 #define MSCAN_BUF_EXT_RTR 0x01
195 #define MSCAN_BUF_EXTENDED 0x08
196 
197 #define MSCAN_IDAM1 0x20
198 /* Value for the interrupt enable register */
199 #define MSCAN_RIER (MSCAN_OVRIE | \
200  MSCAN_RXFIE | \
201  MSCAN_WUPIF | \
202  MSCAN_CSCIE | \
203  MSCAN_RSTATE0 | \
204  MSCAN_RSTATE1 | \
205  MSCAN_TSTATE0 | \
206  MSCAN_TSTATE1)
207 
208 #define BTR0_BRP_MASK 0x3f
209 #define BTR0_SJW_SHIFT 6
210 #define BTR0_SJW_MASK (0x3 << BTR0_SJW_SHIFT)
211 
212 #define BTR1_TSEG1_MASK 0xf
213 #define BTR1_TSEG2_SHIFT 4
214 #define BTR1_TSEG2_MASK (0x7 << BTR1_TSEG2_SHIFT)
215 #define BTR1_SAM_SHIFT 7
216 
217 #define BTR0_SET_BRP(brp) (((brp) - 1) & BTR0_BRP_MASK)
218 #define BTR0_SET_SJW(sjw) ((((sjw) - 1) << BTR0_SJW_SHIFT) & \
219  BTR0_SJW_MASK)
220 
221 #define BTR1_SET_TSEG1(tseg1) (((tseg1) - 1) & BTR1_TSEG1_MASK)
222 #define BTR1_SET_TSEG2(tseg2) ((((tseg2) - 1) << BTR1_TSEG2_SHIFT) & \
223  BTR1_TSEG2_MASK)
224 #define BTR1_SET_SAM(sam) (((sam) & 1) << BTR1_SAM_SHIFT)
225 
226 #endif /* __RTCAN_MSCAN_REGS_H_ */