Xenomai  3.0.8
rtcan_sja1000_regs.h
1 /*
2  * Copyright (C) 2005,2006 Sebastian Smolorz
3  * <Sebastian.Smolorz@stud.uni-hannover.de>
4  *
5  * Based on drivers/can/sja1000.h in linux-can.patch, a CAN socket
6  * framework for Linux:
7  *
8  * Copyright (C) 2005, Sascha Hauer, Pengutronix
9  *
10  *
11  * This program is free software; you can redistribute it and/or modify it
12  * under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful, but
17  * WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19  * General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24  */
25 
26 #ifndef __SJA1000_REGS_H_
27 #define __SJA1000_REGS_H_
28 
29 
30 /* PeliCAN mode address map */
31 
32 /* reset and operating mode */
33 #define SJA_MOD 0 /* Mode register */
34 #define SJA_CMR 1 /* Command register */
35 #define SJA_SR 2 /* Status register */
36 #define SJA_IR 3 /* Interrupt register */
37 #define SJA_IER 4 /* Interrupt enable register */
38 #define SJA_BTR0 6 /* Bus timing register 0 */
39 #define SJA_BTR1 7 /* Bus timing register 1 */
40 #define SJA_OCR 8 /* Output control register */
41 #define SJA_ALC 11 /* Arbitration lost capture */
42 #define SJA_ECC 12 /* Error code capture register */
43 #define SJA_RXERR 14 /* Receive error counter */
44 #define SJA_TXERR 15 /* Transmit error counter */
45 #define SJA_CDR 31 /* Clock divider register */
46 
47 /* reset mode */
48 #define SJA_ACR0 16 /* Acceptance code register 0 */
49 #define SJA_ACR1 17 /* Acceptance code register 1 */
50 #define SJA_ACR2 18 /* Acceptance code register 2 */
51 #define SJA_ACR3 19 /* Acceptance code register 3 */
52 #define SJA_AMR0 20 /* Acceptance mask register 0 */
53 #define SJA_AMR1 21 /* Acceptance mask register 1 */
54 #define SJA_AMR2 22 /* Acceptance mask register 2 */
55 #define SJA_AMR3 23 /* Acceptance mask register 3 */
56 
57 /* operating mode */
58 #define SJA_FIR 16 /* Frame information register */
59 #define SJA_ID1 17 /* Identifier 1 */
60 #define SJA_ID2 18 /* Identifier 2 */
61 #define SJA_ID3 19 /* Identifier 3 (EFF only) */
62 #define SJA_ID4 20 /* Identifier 4 (EFF only) */
63 
64 #define SJA_DATA_SFF(x) (19 + (x)) /* Data registers in case of standard
65  * frame format; 0 <= x <= 7 */
66 #define SJA_DATA_EFF(x) (21 + (x)) /* Data registers in case of extended
67  * frame format; 0 <= x <= 7 */
68 
69 /* Mode register */
70 enum SJA1000_PELI_MOD {
71  SJA_MOD_RM = 1, /* Reset Mode */
72  SJA_MOD_LOM = 1<<1, /* Listen Only Mode */
73  SJA_MOD_STM = 1<<2, /* Self Test Mode */
74  SJA_MOD_AFM = 1<<3, /* Acceptance Filter Mode */
75  SJA_MOD_SM = 1<<4 /* Sleep Mode */
76 };
77 
78 /* Command register */
79 enum SJA1000_PELI_CMR {
80  SJA_CMR_TR = 1, /* Transmission request */
81  SJA_CMR_AT = 1<<1, /* Abort Transmission */
82  SJA_CMR_RRB = 1<<2, /* Release Receive Buffer */
83  SJA_CMR_CDO = 1<<3, /* Clear Data Overrun */
84  SJA_CMR_SRR = 1<<4 /* Self reception request */
85 };
86 
87 /* Status register */
88 enum SJA1000_PELI_SR {
89  SJA_SR_RBS = 1, /* Receive Buffer Status */
90  SJA_SR_DOS = 1<<1, /* Data Overrun Status */
91  SJA_SR_TBS = 1<<2, /* Transmit Buffer Status */
92  SJA_SR_ES = 1<<6, /* Error Status */
93  SJA_SR_BS = 1<<7 /* Bus Status */
94 };
95 
96 /* Interrupt register */
97 enum SJA1000_PELI_IR {
98  SJA_IR_RI = 1, /* Receive Interrupt */
99  SJA_IR_TI = 1<<1, /* Transmit Interrupt */
100  SJA_IR_EI = 1<<2, /* Error Warning Interrupt */
101  SJA_IR_DOI = 1<<3, /* Data Overrun Interrupt */
102  SJA_IR_WUI = 1<<4, /* Wake-Up Interrupt */
103  SJA_IR_EPI = 1<<5, /* Error Passive Interrupt */
104  SJA_IR_ALI = 1<<6, /* Arbitration Lost Interrupt */
105  SJA_IR_BEI = 1<<7, /* Bus Error Interrupt */
106 };
107 
108 /* Interrupt enable register */
109 enum SJA1000_PELI_IER {
110  SJA_IER_RIE = 1, /* Receive Interrupt Enable */
111  SJA_IER_TIE = 1<<1, /* Transmit Interrupt Enable */
112  SJA_IER_EIE = 1<<2, /* Error Warning Interrupt Enable */
113  SJA_IER_DOIE = 1<<3, /* Data Overrun Interrupt Enable */
114  SJA_IER_WUIE = 1<<4, /* Wake-Up Interrupt Enable */
115  SJA_IER_EPIE = 1<<5, /* Error Passive Interrupt Enable */
116  SJA_IER_ALIE = 1<<6, /* Arbitration Lost Interrupt Enable */
117  SJA_IER_BEIE = 1<<7, /* Bus Error Interrupt Enable */
118 };
119 
120 /* Bus timing register 0 */
121 enum SJA1000_PELI_BTR0 {
122  /* Period of the CAN system clock t_SCl
123  * (t_CLK = time period of XTAL frequency) */
124  SJA_BTR0_T_SCL_2_T_CLK = 0, /* t_SCl = 2 x t_CLK */
125  SJA_BTR0_T_SCL_4_T_CLK = 1, /* t_SCl = 4 x t_CLK */
126  SJA_BTR0_T_SCL_6_T_CLK = 2, /* t_SCl = 6 x t_CLK */
127  SJA_BTR0_T_SCL_8_T_CLK = 3, /* t_SCl = 8 x t_CLK */
128  SJA_BTR0_T_SCL_10_T_CLK = 4, /* t_SCl = 10 x t_CLK */
129  SJA_BTR0_T_SCL_12_T_CLK = 5, /* t_SCl = 12 x t_CLK */
130  SJA_BTR0_T_SCL_14_T_CLK = 6, /* t_SCl = 14 x t_CLK */
131  SJA_BTR0_T_SCL_16_T_CLK = 7, /* t_SCl = 16 x t_CLK */
132  SJA_BTR0_T_SCL_20_T_CLK = 9, /* t_SCl = 20 x t_CLK */
133  SJA_BTR0_T_SCL_40_T_CLK = 19, /* t_SCl = 40 x t_CLK */
134  SJA_BTR0_T_SCL_100_T_CLK = 49, /* t_SCl = 100 x t_CLK */
135 
136 };
137 
138 /* Bus timing register 1 */
139 enum SJA1000_PELI_BTR1 {
140  /* Time segment 1 */
141  SJA_BTR1_T_SEG1_1_T_SCL = 0, /* t_SEG1 = 1 x t_SCl */
142  SJA_BTR1_T_SEG1_2_T_SCL = 1, /* t_SEG1 = 2 x t_SCl */
143  SJA_BTR1_T_SEG1_3_T_SCL = 2, /* t_SEG1 = 3 x t_SCl */
144  SJA_BTR1_T_SEG1_4_T_SCL = 3, /* t_SEG1 = 4 x t_SCl */
145  SJA_BTR1_T_SEG1_5_T_SCL = 4, /* t_SEG1 = 5 x t_SCl */
146  SJA_BTR1_T_SEG1_6_T_SCL = 5, /* t_SEG1 = 6 x t_SCl */
147  SJA_BTR1_T_SEG1_7_T_SCL = 6, /* t_SEG1 = 7 x t_SCl */
148  SJA_BTR1_T_SEG1_8_T_SCL = 7, /* t_SEG1 = 8 x t_SCl */
149  /* Time segment 2 */
150  SJA_BTR1_T_SEG2_1_T_SCL = 0<<4, /* t_SEG2 = 1 x t_SCl */
151  SJA_BTR1_T_SEG2_2_T_SCL = 1<<4, /* t_SEG2 = 2 x t_SCl */
152  SJA_BTR1_T_SEG2_3_T_SCL = 2<<4, /* t_SEG2 = 3 x t_SCl */
153  SJA_BTR1_T_SEG2_4_T_SCL = 3<<4, /* t_SEG2 = 4 x t_SCl */
154  SJA_BTR1_T_SEG2_5_T_SCL = 4<<4, /* t_SEG2 = 5 x t_SCl */
155  SJA_BTR1_T_SEG2_6_T_SCL = 5<<4, /* t_SEG2 = 6 x t_SCl */
156  SJA_BTR1_T_SEG2_7_T_SCL = 6<<4, /* t_SEG2 = 7 x t_SCl */
157  SJA_BTR1_T_SEG2_8_T_SCL = 7<<4, /* t_SEG2 = 8 x t_SCl */
158 };
159 
160 /* One bit time = t_SCl + t_SEG1 + t_SEG2 */
161 
162 
163 /* Output control register */
164 enum SJA1000_PELI_OCR {
165  SJA_OCR_MODE_BIPHASE = 0,
166  SJA_OCR_MODE_TEST = 1,
167  SJA_OCR_MODE_NORMAL = 2,
168  SJA_OCR_MODE_CLOCK = 3,
169  SJA_OCR_TX0_INVERT = 1<<2,
170  SJA_OCR_TX0_PULLDOWN = 1<<3,
171  SJA_OCR_TX0_PULLUP = 2<<3,
172  SJA_OCR_TX0_PUSHPULL = 3<<3,
173  SJA_OCR_TX1_INVERT = 1<<5,
174  SJA_OCR_TX1_PULLDOWN = 1<<6,
175  SJA_OCR_TX1_PULLUP = 2<<6,
176  SJA_OCR_TX1_PUSHPULL = 3<<6
177 };
178 
179 /* Error code capture register */
180 enum SJA1000_PELI_ECC {
181  /* The segmentation field gives information about the location of
182  * errors on the bus */
183  SJA_ECC_SEG_MASK = 31, /* Segmentation field mask */
184  SJA_ECC_DIR = 1<<5, /* Transfer direction */
185  SJA_ECC_ERR_BIT = 0<<6,
186  SJA_ECC_ERR_FORM = 1<<6,
187  SJA_ECC_ERR_STUFF = 2<<6,
188  SJA_ECC_ERR_MASK = 3<<6 /* Error code mask */
189 };
190 
191 /* Frame information register */
192 enum SJA1000_PELI_FIR {
193  SJA_FIR_DLC_MASK = 15, /* Data length code mask */
194  SJA_FIR_RTR = 1<<6, /* Remote transmission request */
195  SJA_FIR_EFF = 1<<7 /* Extended frame format */
196 };
197 
198 /* Clock divider register */
199 enum SJA1000_PELI_CDR {
200  SJA_CDR_CLKOUT_MASK = 0x07,
201  SJA_CDR_CLK_OFF = 1<<3, /* Clock off (CLKOUT pin) */
202  SJA_CDR_CBP = 1<<6, /* CAN input comparator bypass */
203  SJA_CDR_CAN_MODE = 1<<7 /* CAN mode: 1 = PeliCAN */
204 };
205 
206 #endif /* __SJA1000_REGS_H_ */