Xenomai  3.0.8
tulip.h
1 /*
2  drivers/net/tulip/tulip.h
3 
4  Copyright 2000,2001 The Linux Kernel Team
5  Written/copyright 1994-2001 by Donald Becker.
6 
7  This software may be used and distributed according to the terms
8  of the GNU General Public License, incorporated herein by reference.
9 
10  Please refer to Documentation/DocBook/tulip.{pdf,ps,html}
11  for more information on this driver, or visit the project
12  Web page at http://sourceforge.net/projects/tulip/
13 
14 */
15 /* Ported to RTnet by Wittawat Yamwong <wittawat@web.de> */
16 
17 #ifndef __NET_TULIP_H__
18 #define __NET_TULIP_H__
19 
20 #include <linux/kernel.h>
21 #include <linux/types.h>
22 #include <linux/spinlock.h>
23 #include <linux/netdevice.h>
24 #include <linux/timer.h>
25 #include <linux/delay.h>
26 #include <asm/io.h>
27 #include <asm/irq.h>
28 
29 #include <rtnet_port.h>
30 
31 
32 
33 /* undefine, or define to various debugging levels (>4 == obscene levels) */
34 #define TULIP_DEBUG 1
35 
36 /* undefine USE_IO_OPS for MMIO, define for PIO */
37 #ifdef CONFIG_TULIP_MMIO
38 # undef USE_IO_OPS
39 #else
40 # define USE_IO_OPS 1
41 #endif
42 
43 
44 
45 struct tulip_chip_table {
46  char *chip_name;
47  unsigned int io_size;
48  int valid_intrs; /* CSR7 interrupt enable settings */
49  int flags;
50 };
51 
52 
53 enum tbl_flag {
54  HAS_MII = 0x0001,
55  HAS_MEDIA_TABLE = 0x0002,
56  CSR12_IN_SROM = 0x0004,
57  ALWAYS_CHECK_MII = 0x0008,
58  HAS_ACPI = 0x0010,
59  MC_HASH_ONLY = 0x0020, /* Hash-only multicast filter. */
60  HAS_PNICNWAY = 0x0080,
61  HAS_NWAY = 0x0040, /* Uses internal NWay xcvr. */
62  HAS_INTR_MITIGATION = 0x0100,
63  IS_ASIX = 0x0200,
64  HAS_8023X = 0x0400,
65  COMET_MAC_ADDR = 0x0800,
66  HAS_PCI_MWI = 0x1000,
67 };
68 
69 
70 /* chip types. careful! order is VERY IMPORTANT here, as these
71  * are used throughout the driver as indices into arrays */
72 /* Note 21142 == 21143. */
73 enum chips {
74  DC21040 = 0,
75  DC21041 = 1,
76  DC21140 = 2,
77  DC21142 = 3, DC21143 = 3,
78  LC82C168,
79  MX98713,
80  MX98715,
81  MX98725,
82  AX88140,
83  PNIC2,
84  COMET,
85  COMPEX9881,
86  I21145,
87  DM910X,
88 };
89 
90 
91 enum MediaIs {
92  MediaIsFD = 1,
93  MediaAlwaysFD = 2,
94  MediaIsMII = 4,
95  MediaIsFx = 8,
96  MediaIs100 = 16
97 };
98 
99 
100 /* Offsets to the Command and Status Registers, "CSRs". All accesses
101  must be longword instructions and quadword aligned. */
102 enum tulip_offsets {
103  CSR0 = 0,
104  CSR1 = 0x08,
105  CSR2 = 0x10,
106  CSR3 = 0x18,
107  CSR4 = 0x20,
108  CSR5 = 0x28,
109  CSR6 = 0x30,
110  CSR7 = 0x38,
111  CSR8 = 0x40,
112  CSR9 = 0x48,
113  CSR10 = 0x50,
114  CSR11 = 0x58,
115  CSR12 = 0x60,
116  CSR13 = 0x68,
117  CSR14 = 0x70,
118  CSR15 = 0x78,
119 };
120 
121 /* register offset and bits for CFDD PCI config reg */
122 enum pci_cfg_driver_reg {
123  CFDD = 0x40,
124  CFDD_Sleep = (1 << 31),
125  CFDD_Snooze = (1 << 30),
126 };
127 
128 
129 /* The bits in the CSR5 status registers, mostly interrupt sources. */
130 enum status_bits {
131  TimerInt = 0x800,
132  SytemError = 0x2000,
133  TPLnkFail = 0x1000,
134  TPLnkPass = 0x10,
135  NormalIntr = 0x10000,
136  AbnormalIntr = 0x8000,
137  RxJabber = 0x200,
138  RxDied = 0x100,
139  RxNoBuf = 0x80,
140  RxIntr = 0x40,
141  TxFIFOUnderflow = 0x20,
142  TxJabber = 0x08,
143  TxNoBuf = 0x04,
144  TxDied = 0x02,
145  TxIntr = 0x01,
146 };
147 
148 
149 enum tulip_mode_bits {
150  TxThreshold = (1 << 22),
151  FullDuplex = (1 << 9),
152  TxOn = 0x2000,
153  AcceptBroadcast = 0x0100,
154  AcceptAllMulticast = 0x0080,
155  AcceptAllPhys = 0x0040,
156  AcceptRunt = 0x0008,
157  RxOn = 0x0002,
158  RxTx = (TxOn | RxOn),
159 };
160 
161 
162 enum tulip_busconfig_bits {
163  MWI = (1 << 24),
164  MRL = (1 << 23),
165  MRM = (1 << 21),
166  CALShift = 14,
167  BurstLenShift = 8,
168 };
169 
170 
171 /* The Tulip Rx and Tx buffer descriptors. */
172 struct tulip_rx_desc {
173  s32 status;
174  s32 length;
175  u32 buffer1;
176  u32 buffer2;
177 };
178 
179 
180 struct tulip_tx_desc {
181  s32 status;
182  s32 length;
183  u32 buffer1;
184  u32 buffer2; /* We use only buffer 1. */
185 };
186 
187 
188 enum desc_status_bits {
189  DescOwned = 0x80000000,
190  RxDescFatalErr = 0x8000,
191  RxWholePkt = 0x0300,
192 };
193 
194 
195 enum t21041_csr13_bits {
196  csr13_eng = (0xEF0<<4), /* for eng. purposes only, hardcode at EF0h */
197  csr13_aui = (1<<3), /* clear to force 10bT, set to force AUI/BNC */
198  csr13_cac = (1<<2), /* CSR13/14/15 autoconfiguration */
199  csr13_srl = (1<<0), /* When reset, resets all SIA functions, machines */
200 
201  csr13_mask_auibnc = (csr13_eng | csr13_aui | csr13_srl),
202  csr13_mask_10bt = (csr13_eng | csr13_srl),
203 };
204 
205 enum t21143_csr6_bits {
206  csr6_sc = (1<<31),
207  csr6_ra = (1<<30),
208  csr6_ign_dest_msb = (1<<26),
209  csr6_mbo = (1<<25),
210  csr6_scr = (1<<24), /* scramble mode flag: can't be set */
211  csr6_pcs = (1<<23), /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
212  csr6_ttm = (1<<22), /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
213  csr6_sf = (1<<21), /* Store and forward. If set ignores TR bits */
214  csr6_hbd = (1<<19), /* Heart beat disable. Disables SQE function in 10baseT */
215  csr6_ps = (1<<18), /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
216  csr6_ca = (1<<17), /* Collision Offset Enable. If set uses special algorithm in low collision situations */
217  csr6_trh = (1<<15), /* Transmit Threshold high bit */
218  csr6_trl = (1<<14), /* Transmit Threshold low bit */
219 
220  /***************************************************************
221  * This table shows transmit threshold values based on media *
222  * and these two registers (from PNIC1 & 2 docs) Note: this is *
223  * all meaningless if sf is set. *
224  ***************************************************************/
225 
226  /***********************************
227  * (trh,trl) * 100BaseTX * 10BaseT *
228  ***********************************
229  * (0,0) * 128 * 72 *
230  * (0,1) * 256 * 96 *
231  * (1,0) * 512 * 128 *
232  * (1,1) * 1024 * 160 *
233  ***********************************/
234 
235  csr6_fc = (1<<12), /* Forces a collision in next transmission (for testing in loopback mode) */
236  csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
237  csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
238  /* set both and you get (PHY) loopback */
239  csr6_fd = (1<<9), /* Full duplex mode, disables hearbeat, no loopback */
240  csr6_pm = (1<<7), /* Pass All Multicast */
241  csr6_pr = (1<<6), /* Promiscuous mode */
242  csr6_sb = (1<<5), /* Start(1)/Stop(0) backoff counter */
243  csr6_if = (1<<4), /* Inverse Filtering, rejects only addresses in address table: can't be set */
244  csr6_pb = (1<<3), /* Pass Bad Frames, (1) causes even bad frames to be passed on */
245  csr6_ho = (1<<2), /* Hash-only filtering mode: can't be set */
246  csr6_hp = (1<<0), /* Hash/Perfect Receive Filtering Mode: can't be set */
247 
248  csr6_mask_capture = (csr6_sc | csr6_ca),
249  csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
250  csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
251  csr6_mask_hdcaptt = (csr6_mask_hdcap | csr6_trh | csr6_trl),
252  csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
253  csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
254  csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
255  csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
256 };
257 
258 
259 /* Keep the ring sizes a power of two for efficiency.
260  Making the Tx ring too large decreases the effectiveness of channel
261  bonding and packet priority.
262  There are no ill effects from too-large receive rings. */
263 #define TX_RING_SIZE 16
264 #define RX_RING_SIZE 8 /* RTnet: RX_RING_SIZE*2 rtskbs will be preallocated */
265 
266 #define MEDIA_MASK 31
267 
268 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
269 
270 #define TULIP_MIN_CACHE_LINE 8 /* in units of 32-bit words */
271 
272 #if defined(__sparc__) || defined(__hppa__)
273 /* The UltraSparc PCI controllers will disconnect at every 64-byte
274  * crossing anyways so it makes no sense to tell Tulip to burst
275  * any more than that.
276  */
277 #define TULIP_MAX_CACHE_LINE 16 /* in units of 32-bit words */
278 #else
279 #define TULIP_MAX_CACHE_LINE 32 /* in units of 32-bit words */
280 #endif
281 
282 
283 /* Ring-wrap flag in length field, use for last ring entry.
284  0x01000000 means chain on buffer2 address,
285  0x02000000 means use the ring start address in CSR2/3.
286  Note: Some work-alike chips do not function correctly in chained mode.
287  The ASIX chip works only in chained mode.
288  Thus we indicates ring mode, but always write the 'next' field for
289  chained mode as well.
290 */
291 #define DESC_RING_WRAP 0x02000000
292 
293 
294 #define EEPROM_SIZE 128 /* 2 << EEPROM_ADDRLEN */
295 
296 
297 #define RUN_AT(x) (jiffies + (x))
298 
299 #if defined(__i386__) /* AKA get_unaligned() */
300 #define get_u16(ptr) (*(u16 *)(ptr))
301 #else
302 #define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
303 #endif
304 
305 struct medialeaf {
306  u8 type;
307  u8 media;
308  unsigned char *leafdata;
309 };
310 
311 
312 struct mediatable {
313  u16 defaultmedia;
314  u8 leafcount;
315  u8 csr12dir; /* General purpose pin directions. */
316  unsigned has_mii:1;
317  unsigned has_nonmii:1;
318  unsigned has_reset:6;
319  u32 csr15dir;
320  u32 csr15val; /* 21143 NWay setting. */
321  struct medialeaf mleaf[0];
322 };
323 
324 
325 struct mediainfo {
326  struct mediainfo *next;
327  int info_type;
328  int index;
329  unsigned char *info;
330 };
331 
332 struct ring_info {
333  struct /*RTnet*/rtskb *skb;
334  dma_addr_t mapping;
335 };
336 
337 
338 struct tulip_private {
339  const char *product_name;
340  /*RTnet*/struct rtnet_device *next_module;
341  struct tulip_rx_desc *rx_ring;
342  struct tulip_tx_desc *tx_ring;
343  dma_addr_t rx_ring_dma;
344  dma_addr_t tx_ring_dma;
345  /* The saved address of a sent-in-place packet/buffer, for skfree(). */
346  struct ring_info tx_buffers[TX_RING_SIZE];
347  /* The addresses of receive-in-place skbuffs. */
348  struct ring_info rx_buffers[RX_RING_SIZE];
349  u16 setup_frame[96]; /* Pseudo-Tx frame to init address table. */
350  int chip_id;
351  int revision;
352  int flags;
353  struct net_device_stats stats;
354  u32 mc_filter[2];
355  /*RTnet*/rtdm_lock_t lock;
356  spinlock_t mii_lock;
357  unsigned int cur_rx, cur_tx; /* The next free ring entry */
358  unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
359 
360 #ifdef CONFIG_NET_HW_FLOWCONTROL
361 #define RX_A_NBF_STOP 0xffffff3f /* To disable RX and RX-NOBUF ints. */
362  int fc_bit;
363  int mit_sel;
364  int mit_change; /* Signal for Interrupt Mitigtion */
365 #endif
366  unsigned int full_duplex:1; /* Full-duplex operation requested. */
367  unsigned int full_duplex_lock:1;
368  unsigned int fake_addr:1; /* Multiport board faked address. */
369  unsigned int default_port:4; /* Last dev->if_port value. */
370  unsigned int media2:4; /* Secondary monitored media port. */
371  unsigned int medialock:1; /* Don't sense media type. */
372  unsigned int mediasense:1; /* Media sensing in progress. */
373  unsigned int nway:1, nwayset:1; /* 21143 internal NWay. */
374  unsigned int csr0; /* CSR0 setting. */
375  unsigned int csr6; /* Current CSR6 control settings. */
376  unsigned char eeprom[EEPROM_SIZE]; /* Serial EEPROM contents. */
377  void (*link_change) (/*RTnet*/struct rtnet_device *rtdev, int csr5);
378  u16 sym_advertise, mii_advertise; /* NWay capabilities advertised. */
379  u16 lpar; /* 21143 Link partner ability. */
380  u16 advertising[4];
381  signed char phys[4], mii_cnt; /* MII device addresses. */
382  struct mediatable *mtable;
383  int cur_index; /* Current media index. */
384  int saved_if_port;
385  struct pci_dev *pdev;
386  int ttimer;
387  int susp_rx;
388  unsigned long nir;
389  unsigned long base_addr;
390  int pad0, pad1; /* Used for 8-byte alignment */
391  rtdm_irq_t irq_handle;
392 };
393 
394 
395 struct eeprom_fixup {
396  char *name;
397  unsigned char addr0;
398  unsigned char addr1;
399  unsigned char addr2;
400  u16 newtable[32]; /* Max length below. */
401 };
402 
403 
404 /* 21142.c */
405 extern u16 t21142_csr14[];
406 void t21142_start_nway(/*RTnet*/struct rtnet_device *rtdev);
407 void t21142_lnk_change(/*RTnet*/struct rtnet_device *rtdev, int csr5);
408 
409 
410 /* PNIC2.c */
411 void pnic2_lnk_change(/*RTnet*/struct rtnet_device *rtdev, int csr5);
412 void pnic2_start_nway(/*RTnet*/struct rtnet_device *rtdev);
413 void pnic2_lnk_change(/*RTnet*/struct rtnet_device *rtdev, int csr5);
414 
415 /* eeprom.c */
416 void tulip_parse_eeprom(struct rtnet_device *rtdev);
417 int tulip_read_eeprom(long ioaddr, int location, int addr_len);
418 
419 /* interrupt.c */
420 extern unsigned int tulip_max_interrupt_work;
421 extern int tulip_rx_copybreak;
422 int tulip_interrupt(rtdm_irq_t *irq_handle);
423 int tulip_refill_rx(/*RTnet*/struct rtnet_device *rtdev);
424 
425 /* media.c */
426 int tulip_mdio_read(struct rtnet_device *dev, int phy_id, int location);
427 void tulip_mdio_write(struct rtnet_device *dev, int phy_id, int location, int value);
428 void tulip_select_media(struct rtnet_device *dev, int startup);
429 int tulip_check_duplex(struct rtnet_device *dev);
430 void tulip_find_mii (struct rtnet_device *dev, int board_idx);
431 
432 /* pnic.c */
433 void pnic_do_nway(/*RTnet*/struct rtnet_device *rtdev);
434 void pnic_lnk_change(/*RTnet*/struct rtnet_device *rtdev, int csr5);
435 
436 /* tulip_core.c */
437 extern int tulip_debug;
438 extern const char * const medianame[];
439 extern const char tulip_media_cap[];
440 extern struct tulip_chip_table tulip_tbl[];
441 extern u8 t21040_csr13[];
442 extern u16 t21041_csr13[];
443 extern u16 t21041_csr14[];
444 extern u16 t21041_csr15[];
445 
446 #ifndef USE_IO_OPS
447 #undef inb
448 #undef inw
449 #undef inl
450 #undef outb
451 #undef outw
452 #undef outl
453 #define inb(addr) readb((void*)(addr))
454 #define inw(addr) readw((void*)(addr))
455 #define inl(addr) readl((void*)(addr))
456 #define outb(val,addr) writeb((val), (void*)(addr))
457 #define outw(val,addr) writew((val), (void*)(addr))
458 #define outl(val,addr) writel((val), (void*)(addr))
459 #endif /* !USE_IO_OPS */
460 
461 
462 
463 static inline void tulip_start_rxtx(struct tulip_private *tp)
464 {
465  long ioaddr = tp->base_addr;
466  outl(tp->csr6 | RxTx, ioaddr + CSR6);
467  barrier();
468  (void) inl(ioaddr + CSR6); /* mmio sync */
469 }
470 
471 static inline void tulip_stop_rxtx(struct tulip_private *tp)
472 {
473  long ioaddr = tp->base_addr;
474  u32 csr6 = inl(ioaddr + CSR6);
475 
476  if (csr6 & RxTx) {
477  outl(csr6 & ~RxTx, ioaddr + CSR6);
478  barrier();
479  (void) inl(ioaddr + CSR6); /* mmio sync */
480  }
481 }
482 
483 static inline void tulip_restart_rxtx(struct tulip_private *tp)
484 {
485  tulip_stop_rxtx(tp);
487  tulip_start_rxtx(tp);
488 }
489 
490 #endif /* __NET_TULIP_H__ */
void rtdm_task_busy_sleep(nanosecs_rel_t delay)
Busy-wait a specified amount of time.
Definition: drvlib.c:483
ipipe_spinlock_t rtdm_lock_t
Lock variable.
Definition: driver.h:551